Rochester Electronics AM79865JC-G

The Physical Data Transmitter (Am79865) and the Physical Data Receiver (Am79866) devices provide clock recovery/generation functions meeting the requirements of FDDl, TP-FDDl, and 100BASE-TX PHY standards. The PDT and PDR devices are part of the SUPERNET 2 FDDl Physical Layer Protocol chip set which also includes the Physical Layer Controller with Scrambler (PLC-S). The PLC-S (Am79C864A), PDT and PDR devices are collectively known as the AmPHY. The PLC-S performs the FDDl physical layer functions which includes, among others, the 4B5B encoding and decoding. The PDT converts encoded symbols into a serial NRZI data stream. The on-chip PLL generates a bit rate clock from the LSCLK reference. The PDR uses a built-in clock recovery PLL to extract clock information from the received data stream. The recovered clock is used for serial-to-parallel data conversion.

• Fully compliant with ANSI X3T9.5 FDDl, TP-FDDI, and 100BASE-TX/FX PHY standards
• Provides data and clock recovery functions for FDDl and Fast Ethernet applications
• Parallel input to the PDT is a 5-bit encoded NRZ symbol clocked by LSCLK
• Parallel output from the PDR is a 5-bit unframed NRZ symbol clocked by RSCLK
• The on-chip Phase-Locked-Loop (PLL) only requires an external frequency reference
• 125 MBaud (100 Mbps) serial link data rate
• Interfaces to fiber or copper media
• Dedicated pins provide electrical loopback datapath
• 20-pin Plastic Leaded Chip Carrier (PLCC)
• Single +5V power supply operation