RENESAS 9DBU0841AKLFT
| Hersteller | |
| Herst.-Teilenr. | 9DBU0841AKLFT |
| LCSC-Nr. | C17295902 |
| Verp. | VFQFPN-48(6x6) |
| Kundennummer | |
| Hauptmerkm. | VFQFPN-48(6x6) Application Specific Clock/Timing RoHS |
| Datenblatt | RENESAS 9DBU0841AKLFT |
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | VFQFPN-48(6x6) | |
| Features | - |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS |
| Typ | Beschreibung | |
|---|---|---|
| Verp. | VFQFPN-48(6x6) | |
| Features | - |
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Beschreibung
KI-Übersetzung
The 9DBU0841 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. It has integrated output terminations providing Zo=100Ω for direct connection to 100 transmission lines. The device has 8 output enables for clock management and 3 selectable SMBus addresses.
Merkmale
KI-Übersetzung
- 8 – 1-167MHz Low-Power (LP) HCSL DIF pairs w/Z0=100Ω
- DIF cycle-to-cycle jitter <50ps
- DIF output-to-output skew <80ps
- DIF phase jitter is PCIe Gen1-2-3 compliant
- Very low additive phase jitter in bypass mode
- Direct connection to 100Ω transmission lines; saves 32 resistors compared to standard HCSL outputs
- 53mW typical power consumption in PLL mode; eliminates thermal concerns
- Outputs can optionally be supplied from any voltage between 1.05 and 1.5V; maximum power savings
- Spread Spectrum (SS) compatible; allows SS for EMI reduction
- OE# pins; support DIF power management
- HCSL-compatible differential input; can be driven by common clock sources
- Spread Spectrum tolerant; allows reduction of EMI
- SMBus-selectable features; optimize signal integrity to application: slew rate for each output, differential output amplitude
- Pin/SMBus selectable PLL bandwidth and PLL Bypass; optimize PLL to application
- Outputs blocked until PLL is locked; clean system start-up
- Device contains default configuration; SMBus interface not required for device control
- Three selectable SMBus addresses; multiple devices can easily share an SMBus segment
- 3.3V tolerant SMBus interface works with legacy controllers
- Space saving 48-pin 6x6mm VFQFPN; minimal board space
Anwendungen
KI-Übersetzung
- 1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Nicht vorrätig
Benachrichtigen
Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
| Stk. | E-Preis(Nur als Referenz) | Gesamtbetrag |
|---|---|---|
| 1+ | $ 7.7046 | $ 7.70 |
| 200+ | $ 3.0746 | $ 614.92 |
| 500+ | $ 2.9714 | $ 1485.70 |
| 1,000+ | $ 2.9206 | $ 2920.60 |
Standardgehäuse2500/Full Reel | ||
Besserer Preis bei größerer Menge?
$
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | VFQFPN-48(6x6) | |
| Features | - |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS |
| Typ | Beschreibung | |
|---|---|---|
| Verp. | VFQFPN-48(6x6) | |
| Features | - |
Hilfe & FeedbackÄhnliche Produkte anzeigen (0) >
Beschreibung
KI-Übersetzung
The 9DBU0841 is a member of IDT's 1.5V Ultra-Low-Power (ULP) PCIe family. It has integrated output terminations providing Zo=100Ω for direct connection to 100 transmission lines. The device has 8 output enables for clock management and 3 selectable SMBus addresses.
Merkmale
KI-Übersetzung
- 8 – 1-167MHz Low-Power (LP) HCSL DIF pairs w/Z0=100Ω
- DIF cycle-to-cycle jitter <50ps
- DIF output-to-output skew <80ps
- DIF phase jitter is PCIe Gen1-2-3 compliant
- Very low additive phase jitter in bypass mode
- Direct connection to 100Ω transmission lines; saves 32 resistors compared to standard HCSL outputs
- 53mW typical power consumption in PLL mode; eliminates thermal concerns
- Outputs can optionally be supplied from any voltage between 1.05 and 1.5V; maximum power savings
- Spread Spectrum (SS) compatible; allows SS for EMI reduction
- OE# pins; support DIF power management
- HCSL-compatible differential input; can be driven by common clock sources
- Spread Spectrum tolerant; allows reduction of EMI
- SMBus-selectable features; optimize signal integrity to application: slew rate for each output, differential output amplitude
- Pin/SMBus selectable PLL bandwidth and PLL Bypass; optimize PLL to application
- Outputs blocked until PLL is locked; clean system start-up
- Device contains default configuration; SMBus interface not required for device control
- Three selectable SMBus addresses; multiple devices can easily share an SMBus segment
- 3.3V tolerant SMBus interface works with legacy controllers
- Space saving 48-pin 6x6mm VFQFPN; minimal board space
Anwendungen
KI-Übersetzung
- 1.5V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
C17295902 EasyEDA-Bibliothek
Compliance & Exportcodes
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Typ | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

