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RENESAS 9FGL0641BKILF product image
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RENESAS 9FGL0641BKILF

Manufacturer
MPN
9FGL0641BKILF
LCSC Part #
C17277434
Packaging
VFQFPN-40(5x5)
Customer #
Key Attributes
VFQFPN-40(5x5) Application Specific Clock/Timing RoHS
DatasheetRENESAS 9FGL0641BKILF
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement
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QtyUnit Price(Reference Only)Total Amount
1+$ 18.988$ 18.99
200+$ 7.5764$ 1515.28
490+$ 7.3235$ 3588.52
980+$ 7.1993$ 7055.31
Standard Packaging490/Full Tray
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing
ManufacturerRENESAS
PackagingVFQFPN-40(5x5)
Voltage - Supply3.135V~3.465V;997.5mV~3.465V
FeaturesSleep/Wake control
Frequency100MHz
Input Low Voltage0.8V
Output Low Voltage0.4V
Intput High Voltage2.1V~3.6V
Output High Voltage660mV~850mV
Operating Temperature-40℃~+85℃

Introduction

AI Translation

The 9FGL06 devices are 3.3V members of IDT's 3.3V Full-Featured PCIe family. The devices have 6 output enables for clock management and support 2 different spread spectrum levels in addition to spread off. The 9FGL06 supports PCIe Gen1-4 Common Clocked architectures (CC) and PCIe Separate Reference no-Spread (SRnS) and Separate Reference Independent Spread (SRIS) clocking architectures. The 9FGL06P1 can be programmed with a user-defined power up default SMBus configuration.

Features

AI Translation
  • Direct connection to 100Ω (xx41) or 85Ω (xx51) transmission lines; saves 24 resistors compared to standard PCIe devices
  • 172mW typical power consumption (@3.3V); eliminates thermal concerns
  • SMBus-selectable features allows optimization to customer requirements:
    • control input polarity
    • control input pull up/downs
    • slew rate for each output
    • differential output amplitude
    • 33, 85 or 100Ω output impedance for each output
    • spread spectrum amount
  • 41 and 51 devices contain default configuration; SMBus interface not required for device operation
  • P1 device allows factory programming of customer-defined SMBus power up default; allows exact optimization to customer requirements
  • 8MHz - 40MHz input frequency with 9FGL08P1 device (25MHz default); flexibility
  • OE# pins; support DIF power management
  • Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF outputs; minimize EMI and phase jitter for each application
  • DIF outputs blocked until PLL is locked; clean system start-up
  • Two selectable SMBus addresses; multiple devices can easily share an SMBus segment
  • Space saving 40-pin 5x5mm VFQFPN; minimal board space

Applications

AI Translation
  • PCIe Gen1-4 clock generation for Riser Cards
  • Storage
  • Networking
  • JBOD
  • Communications
  • Access Points