Lattice LPTM21-1AFTG237I

The Lattice Platform Manager 2 device is a fast-reacting, programmable logic based hardware management controller. Platform Manager 2 is an integrated solution combining analog sense and control elements with scalable programmable logic resources. This unique approach allows Platform Manager 2 to integrate Power Management (Power Sequencing, Voltage Monitoring, Trimming and Margining), Thermal Management (Temperature Monitoring, Fan Control, Power Control), and Control Plane functions (System Configuration, I/O Expansion, etc.) as a single device.

Architecturally, the Platform Manager 2 device can be divided into two sections – Analog Sense and Control and FPGA. The Analog Sense and Control (ASC) section provides three types of analog sense channels: voltage (nine standard channels and one high voltage channel), current (one standard voltage and one high voltage) and temperature (two external and one internal).

Each of the analog sense channels is monitored through two independently programmable comparators to support both high/low and in-bounds/out-of-bounds (window-compare) monitor functions. In addition, each of the current sense channels provides a fast fault detect (one µs response time) for detecting short circuit events. The temperature sense channels can be configured to work with different external transistor or diode configurations.

The Analog Sense and Control section also provides ten general purpose 5 V tolerant open-drain digital input/output pins that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and opto-couplers, as well as for general purpose logic interface functions. In addition, four high-voltage charge pumped outputs (HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers to control high-side MOSFET switches. These HVOUT outputs can also be programmed as static output signals or as switched outputs (to support external charge pump implementation) operating at a dedicated duty cycle and frequency.

The ASC section incorporates four TRIM outputs for controlling the output voltages of DC-DC converters. Each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode of the trimming block.

The internal 10-bit A/D converter can be used to measure the voltage and current through the I2C bus. The ADC is also used in the digital closed loop control mode of the trimming block.

The ASC section also provides the capability of logging up to 16 status records into its nonvolatile EEPROM memory. Each record includes voltage, current and temperature monitor signals along with digital input and output levels.

The ASC section includes an output control block (OCB) which allows certain inputs and control signals a direct connection to the digital outputs or HVOUTs, bypassing the ASC-I/F for a faster response. The OCB is used to connect the fast current fault detect signal to an FPGA input directly. It also supports functions such as Hot Swap with a programmable hysteretic controller.

The FPGA section contains non-volatile low cost programmable logic of 1280 Look-Up Tables (LUTs). In addition to the LUT-based logic, the FPGA section features Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), flexible I/Os, and hardened versions of commonly used functions such as SPI controller, I2C controller and Timer/counter. The FPGA I/Os offer enhanced features such as drive strength control, slew rate control, buskeeper latches, internal pull-up or pull-down resistors, and open-drain outputs. These features are controllable on a “per-pin” basis.

The power management, thermal management and control plane logic functions are implemented in the FPGA section of Platform Manager 2. The FPGA receives the analog comparator values and inputs from the ASC section and sends output commands to the ASC section through the dedicated ASC-interface (ASC-I/F) high-speed, reliable serial channel. The FPGA hardware management functions are implemented using the Platform Designer tool inside Lattice Diamond software. The Platform Designer tool includes an easy to use sequence and monitor logic builder tool and a set of pre-engineered components for functions like time-stamped fault logging, voltage by identification (VID), and fan control.

• Ten Rail Voltage Monitoring and Measurement
  • UV/OV Fault Detection Accuracy – 0.2% Typ.
  • Fault Detection Speed <100 µs
  • High Voltage, Single Ended and Differential Sensing
• Two Channel Wide-Range Current Monitoring and Measurement
  • High-side current measurement up to 12 V
  • Programmable OC/UC Fault Detect
  • Detects Current faults in <1 µs
• Three Temperature Monitoring and Measurement Channels
  • Programmable OT/UT Faults Threshold
  • Two channels of Temperature Monitoring using external diodes
  • On-Chip Temperature Monitor
• 4 High-Side MOSFET Drivers
  • Programmable Charge Pump
• FPGA Resources
  • 1280 LUT, 98 I/O Version (LPTM21)
  • 1280 LUT, 33 I/O Version (LPTM21L)
• RAM and Flash Memories Scalable Hardware Management Architecture
  • Glueless interface to Hardware Management Expander (L-ASC10)
  • Migrate between LPTM21 and larger density MachXO2, MachXO3, and ECP5 devices to extend logic and I/O resources
• System Level Support
  • Operating voltage from 2.8 to 3.46 V
  • Industrial and commercial temperature ranges
  • 237-ball ftBGA (LPTM21)
  • 100-ball caBGA (LPTM21L)
  • RoHS compliant and halogen-free

• Telecommunication and Networking
• Industrial, Test and Measurement
• Medical Systems
• Servers and Storage Systems
• High Reliability Systems