Lattice LA4064V-75TN44E

The high performance LA-ispMACH 4000V/Z automotive family offers a SuperFAST CPLD solution that is tested and qualified to the AEC-Q100 standard. The family is a blend of two popular architectures: the ispLS 2000 and ispMACH 4A. Retaining the best of both families, the LA-ispMACH 4000V/Z architecture focuses on significant innovations to combine the highest performance with low power in a flexible CPLD family. The LA-ispMACH 4000V/Z automotive family combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent FirstTime-Fit, timing predictability, routing, pin-out retention and density migration. The LA-ispMACH 4000V/Z automotive family offers densities ranging from 32 to 128 macrocells. There are multiple density-package combinations in Thin Quad Flat Pack (TQFP) packages ranging from 44 to 144 pins. The LA-ispMACH 4000V/Z automotive family has enhanced system integration capabilities. It supports 3.3V (4000V) and 1.8V (4000Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The LA-ispMACH 4000V/Z also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. The LA-ispMACH 4000V/Z automotive family is in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK, TMS, TDI and TDO are referenced to VCC (logic core).

• fMAX = 168MHz maximum operating frequency
• tPD = 7.5ns propagation delay
• Up to four global clock pins with programmable clock polarity control
• Up to 80 PTs per output
• Enhanced macrocells with individual clock, reset, preset and clock enable controls
• Up to four global OE controls
• Individual local OE control per I/O pin
• Excellent First-Time-FitTM and refit
• Fast path, SpeedLockingTM Path, and wide-PT path
• Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
• Typical static current 10μA (4032Z)
• 1.8V core low dynamic power
• LA-ispMACH 4000Z operational down to 1.6V
• Automotive: -40 to 125℃ ambient (TA)
• Superior solution for power sensitive consumer applications
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• Operation with 3.3V (4000V) or 1.8V (4000Z) supplies
• 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Programmable output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V In-System Programmable (ISP) using IEEE 1532 compliant interface
• I/O pins with fast setup path
• Lead-free (RoHS) package