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NXP MPC8347CVRADDB

Manufacturer
MPN
MPC8347CVRADDB
LCSC Part #
C1555439
Packaging
PBGA-620
Customer #
Key Attributes
Freescale Series 266MHz PBGA-620 Microprocessors RoHS
DatasheetNXP MPC8347CVRADDB
RoHS Compliance2 documents available
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Embedded/Microprocessors
ManufacturerNXP
PackagingPBGA-620
Features-
CPU CoreFreescale Series
CPU Maximum Speed266MHz

Introduction

AI Translation

The MPC8347EA PowerQUICC II Pro is a next generation PowerQUICC II integrated host processor. The MPC8347EA contains a processor core built on Power Architecture technology with system logic for networking, storage, and general-purpose embedded applications.

Features

AI Translation
  • Embedded PowerPC e300 processor core; operates at up to 667 MHz
  • High-performance, superscalar processor core
  • Floating-point, integer, load/store, system register, and branch processing units
  • 32-Kbyte instruction cache, 32-Kbyte data cache
  • Lockable portion of L1 cache
  • Dynamic power management
  • Software-compatible with the other Freescale processor families that implement Power Architecture technology
  • Double data rate, DDR1/DDR2 SDRAM memory controller
  • Programmable timing supporting DDR1 and DDR2 SDRAM
  • 32- or 64-bit data interface, up to 400 MHz data rate for TBGA, 266 MHz for PBGA
  • Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
  • DRAM chip configurations from 64 Mbits to 1 Gbit with ×8/×16 data ports
  • Full error checking and correction (ECC) support
  • Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
  • Contiguous or discontiguous memory mapping
  • Read-modify-write support
  • Sleep-mode support for SDRAM self refresh
  • Auto refresh
  • On-the-fly power management using CKE
  • Registered DIMM support
  • 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
  • Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
  • Dual controllers designed to comply with IEEE 802.3, 802.3u, 820.3x, 802.3z, 802.3ac standards
  • Ethernet physical interfaces: 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex; 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
  • Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100 programming models
  • 9.6-Kbyte jumbo frame support
  • RMON statistics support
  • Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
  • MII management interface for control and status
  • Programmable CRC generation and checking
  • PCI interface
  • Designed to comply with PCI Specification Revision 2.3
  • Data bus width: 32-bit data PCI interface operating at up to 66 MHz
  • PCI 3.3-V compatible
  • PCI host bridge capabilities
  • PCI agent mode on PCI interface
  • PCI-to-memory and memory-to-PCI streaming
  • Memory prefetching of PCI read accesses and support for delayed read transactions
  • Posting of processor-to-PCI and PCI-to-memory writes
  • On-chip arbitration supporting five masters on PCI
  • Accesses to all PCI address spaces
  • Parity supported
  • Selectable hardware-enforced coherency
  • Address translation units for address mapping between host and peripheral
  • Dual address cycle for target
  • Internal configuration registers accessible from PCI
  • Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std. 802.11i, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs)
  • Public key execution unit (PKEU): RSA and Diffie-Hellman algorithms; Programmable field size up to 2048 bits; Elliptic curve cryptography F2m and F(p) modes; Programmable field size up to 511 bits
  • Data encryption standard (DES) execution unit (DEU): DES and 3DES algorithms; Two key (K1, K2) or three key (K1, K2, K3) for 3DES; ECB and CBC modes for both DES and 3DES
  • Advanced encryption standard unit (AESU): Implements the Rijndael symmetric-key cipher; Key lengths of 128, 192, and 256 bits; ECB, CBC, CCM, and counter (CTR) modes; XOR parity generation accelerator for RAID applications
  • ARC four execution unit (AFEU): Stream cipher compatible with the RC4 algorithm; 40- to 128-bit programmable key
  • Message digest execution unit (MDEU): SHA with 160-, 224-, or 256-bit message digest; MD5 with 128-bit message digest; HMAC with either algorithm
  • Random number generator (RNG)
  • Four crypto-channels, each supporting multi-command descriptor chains; Static and/or dynamic assignment

Applications

AI Translation
  • Networking
  • Storage
  • General-purpose embedded
  • RAID applications
  • Applications requiring encryption processing