Intel/Altera EP1AGX35CF484I6N

The Arria GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria GX devices include 4 to 12 high - speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI - Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with the ability to develop proprietary, serial - based IP using its Basic mode. The transceivers build upon the success of the Stratix II GX family. The Arria GX FPGA technology offers a 1.2 - V logic array with the right level of performance and dependability needed to support these mainstream protocols.

• Transceiver block features:
  • High - speed serial transceiver channels with CDR support up to 3.125 Gbps.
  • Devices available with 4, 8, or 12 high - speed full - duplex serial transceiver channels.
  • Support for the following CDR - based bus standards—PCI Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial - based IP using its Basic mode.
  • Individual transmitter and receiver channel power - down capability for reduced power consumption during non - operation.
  • 1.2 - and 1.5 - V pseudo current mode logic (PCML) support on transmitter output buffers.
  • Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode).
  • Hot socketing feature for hot plug - in or hot swap and power sequencing support without the use of external devices.
  • Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial Digital Interface (SDI), and Serial RapidIO.
  • 8B/10B encoder/decoder performs 8 - bit to 10 - bit encoding and 10 - bit to 8 - bit decoding.
  • Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array.
  • Channel aligner compliant with XAUI.
• Main device features:
  • TriMatrix memory consisting of three RAM block sizes to implement true dual - port memory and first - in first - out (FIFO) buffers with performance up to 380 MHz.
  • Up to 16 global clock networks with up to 32 regional clock networks per device.
  • High - speed DSP blocks provide dedicated implementation of multipliers, multiply - accumulate functions, and finite impulse response (FIR) filters.
  • Up to four enhanced phase - locked loops (PLLs) per device provide spread spectrum, programmable bandwidth, clock switch - over, and advanced multiplication and phase shifting.
  • Support for numerous single - ended and differential I/O standards.
  • High - speed source - synchronous differential I/O support on up to 47 channels.
  • Support for source - synchronous bus standards, including SPI - 4 Phase 2 (POS - PHY Level 4), SFI - 4.1, XSBI, UTOPIA IV, NPSI, and CSIX - L1.
  • Support for high - speed external memory including DDR and DDR2 SDRAM, and SDR SDRAM.
  • Support for multiple intellectual property megafunctions from Altera MegaCore functions and Altera Megafunction Partners Program (AMPPSM).
  • Support for remote configuration updates.