TI SN74AS109AD

Package options include plastic small outline (D), ceramic chip carrier (FK), and standard plastic (N) and ceramic (J) 300-mil DIP packages. These devices contain two independent J-K positive-edge-triggered flip-flops. When the preset (PRE) or clear (CLR) inputs are LOW, the outputs are set or reset regardless of the levels of other inputs. When PRE and CLR are inactive (HIGH), data at the J and K inputs that meets setup time requirements is transferred to the outputs on the rising edge of the clock (CLK) pulse. Clock triggering occurs at a specific voltage level and is not directly related to the rise time of the clock pulse. After the hold time interval has elapsed, data at the J and K inputs may change without affecting the output levels. These versatile flip-flops can be configured as toggle flip-flops by tying K LOW and J HIGH, or used as D-type flip-flops when J and K are connected together. NC indicates no internal connection. The logic symbol conforms to ANSI/IEEE Std 91-1984 and IEC Publication 617-12, and the pin numbers shown correspond to the D, J, and N packages. SN74ALS109A and SN74AS109A operate over a temperature range of 0°C to 70°C. SN74ALS109A and SN74AS109A are available in D or N packages.