TI CY74FCT373TSOC

The ’FCT373T devices consist of eight latches with 3 - state outputs for bus - organized applications. When the latch - enable (LE) input is high, the flip - flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output - enable (OE) input is low. When OE is high, the bus output is in the high - impedance state. In this mode, data can be entered into the latches. These devices are fully specified for partial - power - down applications using I₀ff. The I₀ff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

• Function and Pinout Compatible With FCT and F Logic
• Reduced V₀ₕ (Typically = 3.3x) Versions of Equivalent FCT Functions
• Edge - Rate Control Circuitry for Significantly Improved Noise Characteristics
• Iₒff Supports Partial - Power - Down Mode Operation
• ESD Protection Exceeds JESD 22:
  • 2000 - V Human - Body Model (A114 - A)
  • 200 - V Machine Model (A115 - A)
  • 1000 - V Charged - Device Model (C101)
• Matched Rise and Fall Times
• Fully Compatible With TTL Input and Output Logic Levels
• 3 - State Outputs
• CY54FCT373T:
  • 32 - mA Output Sink Current
  • 12 - mA Output Source Current
• CY74FCT373T:
  • 64 - mA Output Sink Current
  • 32 - mA Output Source Current

• bus - organized applications
• partial - power - down applications