RENESAS TSI381-66IL

The IDT Tsi381 is a high-performance bus bridge that connects the PCI Express protocol to the PCI bus standard. The Tsi381’s PCIe Interface supports a x1 lane PCIe configuration, which enables the bridge to offer exceptional throughput performance of up to 2.5 Gbps per transmit and receive direction. The device’s PCI Interface can operate up to 66 MHz. This interface offers designers extensive flexibility by supporting three types of addressing modes: transparent, opaque, and non-transparent. The Tsi381 simplifies board design by using only two power supplies with no power sequencing constraints. Its package is designed to simplify board layout for high reliability and signal integrity. A comprehensive suite of design support resources are also available to aid designers. Pin compatibility with the PLX PEX8111 and PEX8112 make it easy for designers to migrate current designs to the Tsi381, and thereby bring them to market quickly and with low risk. In addition to low-latency operation and high throughput, the Tsi381 incorporates performance enhancing features, such as short-term caching, that can provide a significant performance boost in many applications. Transparent mode operation is available for efficient, flow through configurations, while non-transparent bridging allows isolation between the Tsi381’s PCIe and PCI domains. Non-transparent bridging also enables multi-host systems and is used in applications such as intelligent adapter cards. Opaque mode provides semi-transparent operation for multi-processor configurations and enhanced private device support.

• PCI Express to PCI bridge Transparent, Non-transparent, and Opaque modes
• Efficient queuing and buffering for low latency and high throughput
• Compliant with the following specifications: PCI Express Base 1.1, PCI Express PCI/PCI-X Bridge 1.0, PCI-to-PCI Bridge Architecture 1.2, PCI Local Bus 3.0, PCI Bus Power Management Interface 1.2
• x1 lane PCIe Interface
• Advanced error reporting capability
• End-to-end CRC check and generation
• Up to four outstanding memory reads
• ASPM L0 link state power management
• Legacy interrupt signaling and MSI interrupts
• Hot Plug support
• 32/64-bit addressing and 32-bit data
• Operates at 25, 33, 50, and 66 MHz
• Up to eight outstanding memory reads
• 3.3V PCI I/Os, 5V tolerant
• Four external PCI masters supported through internal arbiter
• MSI generation and handling using interrupt and GPIO signals
• Masquerade mode
• JTAG IEEE 1149.1, 1149.6 to allow testing of the PCIe Interface
• Four GPIO pins and four interrupt pins that can generate MSIs
• D0, D3 hot, D3 cold power management state support
• 1.2V core power supply
• No power sequencing constraints
• Packaging: 13x13 mm, 144-pin PBGA (10x10 mm option is available; part number Tsi382)
• Pinout and footprint compatible with PLX PEX 8111/8112
• Industrial temperature operating range
• RoHS-compliant package available

• Digital video recorders
• Motherboards (server, SBC, industrial PC)
• PC adapter cards (communications, graphics, imaging, and multimedia)
• Multifunction printers
• Line cards and NICs