RENESAS SSTE32882HLBAKG

28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 clock driver with parity, designed for 1.35V and 1.5V VDD operation. All inputs are compatible with 1.35V and 1.5V CMOS, except the RESET and MIRROR inputs, which are LVCMOS. All outputs are 1.35V and 1.5V CMOS edge-rate-controlled drivers optimized for driving single-ended 25Ω to 50Ω traces in DDR3 RDIMM applications, except the open-drain error (ERROUT) output. The clock outputs (Yn and Yn_bar) and control net outputs QnCKEn, QnCSn_bar, and QnODTn are designed with different drive strengths and skews to compensate for varying loads and equalize signal propagation speed.

The SSTE32882HLB has two fundamental operating modes associated with the quad chip select enable (QCSEN) input. When the QCSEN_bar input pin is left floating (or pulled high), the device has two chip select inputs DCS0 and DCS1, with two copies of each chip select output: QACS0, QACS1, QBCS0, and QBCS1_bar. This is "QuadCS Disabled" mode. When the QCSEN_bar input pin is pulled low, the device has four chip select inputs DCS[3:0]_bar and four chip select outputs QxCS[3:0]_bar. This is "QuadCS Enabled" mode. Throughout the remainder of this specification, DCS[n:0]_bar refers to all chip select inputs, where n=1 for QuadCS Disabled and n=3 for QuadCS Enabled. QxCS[n:0]_bar refers to all chip select outputs.

The SSTE32882HLB contains a high-performance, low-jitter, low-skew buffer that distributes the differential clock inputs (CK and CK_bar) to four differential clock output pairs (Yn and Yn_bar) and one feedback clock output pair (FBOUT and FBOUT_bar). The clock outputs are controlled by the input clock (CK and CK_bar), the feedback clock (FBIN and FBIN), and the analog power supply inputs (AVDD and AVSS). When AVDD is grounded, the PLL is disabled and bypassed for test purposes.

The SSTE32882HLB operates from a differential clock (CK and CK_bar). Data is registered at the crossing point of the rising edge of CK and the falling edge of CK_bar. If exactly one DCS[n:0]_bar input signal is asserted low, data is driven to the corresponding device outputs.

Based on control register settings, the device can modify its output characteristics to match different DIMM network topologies. Timing can be adjusted to compensate for different flight times of signals in the target application. Power consumption can be reduced by disabling unused outputs.

The SSTE32882HLB accepts a parity bit from the memory controller on the parity (PAR_IN) input, compares it against data received on the DIMM address inputs (DAn, DBAn, DRAS, DCAS, and DWE), and indicates on the open-drain ERROUT pin (active low) whether a parity error has occurred. Even parity is used; that is, valid parity is defined as an even number of 1s across the combined DIMM address data inputs and the parity input bit. For parity calculation, all DIMM address D inputs must be connected to a known logic state.

DIMM-dependent signals (DCKEn, DODTn, and DCSn) are not included in the parity check calculation.

To ensure deterministic output from the register before a stable clock is provided, RESET must be held low during power-up.

The SSTE32882HLB is available in a 176-ball BGA package with 0.65mm ball pitch arranged in an 11×20 grid. It is also available in a 176-ball fine-pitch thin BGA package with 0.65mm ball pitch arranged in an 8×22 grid. The device pinout places outputs on the outer two columns to facilitate DIMM signal routing. The corresponding input arrangement allows two devices to be placed back-to-back for quad-rank modules while sharing the same vias for data inputs. Each input and output is located adjacent to an associated depopulated ball position or on the outer two rows, enabling the use of low-cost via technology combined with the small 0.65mm ball pitch.

• Pin layout optimized for DDR3 RDIMM PCB routing
• 1-to-2 register outputs and 1-to-4 clock pair outputs support stacked DDR3 RDIMMs
• PLL clock driver buffers one differential clock pair (CK and CK) and distributes to four differential outputs
• Supports LVCMOS switching levels on RESET and MIRROR inputs
• Parity checking on independent DIMM data inputs
• Supports dynamic 1T/3T timing transactions and output inversion to improve timing performance during normal operation and MRS command pass-through
• Supports CKE power-down operating mode
• Supports quad chip select operation feature
• RESET input disables differential input receivers, resets all registers, and disables all output drivers except ERROUT and QnCKEn
• Access to internal control words for device feature configuration and adaptation to various RDIMM and system applications
• Latch performance exceeds 100mA
• ESD > 2000V per MIL-STD883 Method 3015; ESD > 200V using machine model Delta c=200pF, R=0
• 176-ball BGA package