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TI TMDS361BPAG

Fabricant
Réf. Fab.
TMDS361BPAG
Réf. LCSC
C1523154
Condit.
TQFP-64(10x10)
Numéro Client
Caract. clés
3Gbps 3V~3.6V I2C TQFP-64(10x10) Video Processing RoHS
Fiche TechniqueTI TMDS361BPAG
Conformité RoHS1 documents disponibles
Pièces alternatives1
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QtéPrix unit.(Référence uniquement)Montant total
1+$ 2.7105$ 2.71
200+$ 1.0497$ 209.94
500+$ 1.0124$ 506.20
1,000+$ 0.9953$ 995.30
Boîtier Standard160/Full Tray
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Spécifications du Produit

Tout
TypeDescription
CatégorieIntegrated Circuits (ICs)/Linear/Video Processing
FabricantTI
Condit.TQFP-64(10x10)
Data Rate3Gbps
Voltage - Supply3V~3.6V
FeaturesLink equalization and compensation
Operating Temperature0℃~+70℃
Type-
Control InterfaceI2C

Description

Traduction par IA

The TMDS361B is a three-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that allows up to three DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports signaling rates up to 3 Gbps to allow 1080ρ resolution in 16-bit color depth. TMDS361B is not intended for source side applications such as external switch boxes.

The TMDS361B provides an adaptive equalizer for different ranges of cable lengths. The equalizer automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps.

When any of the input ports are selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled, and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.

The TMDS361B is designed to be controlled via a local |²C interface or GPIO interface based on the status of the I2C_SEL pin. The local |²C interface in TMDS361B is a slave-only |²C interface.

Following are some of the key features (advantages) that TMDS361B provides to the overall sink-side system (HDTV). • s×l switch that supports TMDS data rates up to 3 Gbps on all three input ports • ESD: Built-in support for high ESD protection (up to 10 kV on the HDMI source side). The HDMI source-side pins on the TMDS361B are connected via the HDMI/DVI exterior connectors and cable to the HDMI/DVI sources (e.g., DVD player). In TV applications, it can be expected that the source side may be subjected to higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver. • Adaptive equalization: The built-in adaptive equalization support compensates for intersymbol interference [ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Adaptive equalization adjusts the equalization gain automatically, based on the cable length and the incoming TMDS data rate. • TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures that the TMDS output port is turned on only if there is a valid TMDS input signal. TMDS clock-detect feature can be bypassed in ¹²C mode. It is recommended to enable the TMDS clock-detect circuitry during normal operation. However, for HDMI compliance testing (TMDS termination-voltage test), the clock-detect feature should be disabled by using the |²C mode control. If the customer requires passing the TMDS termination-voltage test in GPIO mode with the default TMDS clock-detect circuitry enabled, then a valid TMDS clock should be provided for this compliace test, so that the terminations on the TMDS data pair can be connected, and thus customer can pass the TMDS termination-voltage test. • DDC |²C buffer: This feature provides isolation on the source side

Caractéristiques

Traduction par IA
  • 3:1 Sink-side switch Supporting DVI Above 1920×1200 and HDMI HDTV Resolutions up to 1080p With 16-Bit Color Depth
  • Designed for Signaling Rates up to 3 Gbps
  • Supports HDMI 1.3a Specification
  • Adaptive Equalization on inputs to support up to ≥0-m HDMI Cable at 2.25 Gbps for 1080p 12-Bit Color Depth
  • TMDS Input Clock-Detect Circuit
  • DDC Repeater Function
  • <2-mW Low-Power Mode
  • Local |²C or GPIO Configurable
  • Enhanced ESD. HBM: 10 KV on All Input TMDS, DDC, HPD Pins
  • 3.3-Volt Power Supply
  • Temperature Range: 0°C to 70°C
  • 64-Pin TQFP Package: Pin-Compatible With TMDS351
  • Robust TMDS Receive Stage That Can Work With Non-Compliant Input Common-Mode HDMI Signal

Applications

Traduction par IA
  • High-Definition Digital TV
  • LCD
  • Plasma
  • DLP

Pièces alternatives

MPNFabricantConditionnementDisponibilitéPrix unitaire
TMDS361BPAGRTITQFP-64(10x10)0$ 4.9495