SILICON LABS SI53112-A00AGM

The Si53112 is a low-power, 12-output, differential clock buffer that meets all of the performance requirements of the Intel DB1200ZL specification. The device is optimized for distributing reference clocks for Intel QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output has a dedicated hardware output enable pin for maximum flexibility and power savings.

• Twelve 0.7 V low-power, pushpull, HCSL-compatible PCIe Gen 3 outputs
• Individual OE HW pins for each output clock
• 100 MHz /133 MHz PLL operation, supports PCIe and QPI
• PLL bandwidth SW SMBUS programming overrides the latch value from HW pin
• 9 selectable SMBUS addresses
• SMBus address configurable to allow multiple buffers in a single control network
• 3.3 V supply voltage operation
• PLL or bypass mode
• Spread spectrum tolerable
• 1.05 to 3.3 V I/O supply voltage
• 50 ps output-to-output skew
• 50 ps cyc-cyc jitter (PLL mode)
• Low phase jitter (Intel QPI, PCIe Gen 1/2/3/4 common clock compliant)
• Gen 3 SRNS Compliant
• 100 ps input-to-output delay
• Extended Temperature: –40 to 85 °C
• Package: 64-pin QFN

• Server
• Storage
• Datacenter
• Enterprise Switches and Routers