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SILICON LABS SI53340-B-GM
| Manufacturer | |
| MPN | SI53340-B-GM |
| LCSC Part # | C1520073 |
| Packaging | QFN-16-EP(3x3) |
| Customer # | |
| Key Attributes | Low-Jitter LVDS Fanout Clock Buffers with up to 10 LVDS Outputs from Any-Format Input and Wide Frequency Range from dc
up to 1250 MHz |
| Datasheet | SILICON LABS SI53340-B-GM |
| Alternative Parts | 1 |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers | |
| Manufacturer | SILICON LABS | |
| Packaging | QFN-16-EP(3x3) | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 1.8V;2.5V;3.3V | |
| Features | Output enable/shutdown;Internal termination and bias network | |
| Number of Inputs | 2 | |
| Output Frequency(Max) | 1.25GHz | |
| Number of outputs | 4 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers | |
| Manufacturer | SILICON LABS | |
| Packaging | QFN-16-EP(3x3) | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 1.8V;2.5V;3.3V |
| Type | Description | |
|---|---|---|
| Features | Output enable/shutdown;Internal termination and bias network | |
| Number of Inputs | 2 | |
| Output Frequency(Max) | 1.25GHz | |
| Number of outputs | 4 |
Introduction
The Si53340-45 family of LVDS fanout buffers is ideal for clock/data distribution and redundant clocking applications. These devices feature typical ultra-low jitter of 50 fs and operate over a wide frequency range from dc to 1250 MHz. Built-in LDOs deliver high PSRR performance and reduces the need for external components simplifying low jitter clock distribution in noisy environments. They are available in multiple configurations and offer a selectable input clock using a 2:1 input mux. Other features include independent output enable and built-in format translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance.
Features
- Ultra-low additive jitter: 50 fs rms
- Built-in LDOs for high PSRR performance
- Up to 10 LVDS Outputs
- Any-format Inputs (LVPECL, Low-Power LVPECL, LVDS, CML, HCSL, LVCMOS)
- Wide frequency range: dc to 1250 MHz
- Output Enable option
- Multiple configuration options
- 2:1 Input Mux
- RoHS compliant, Pb-free
- Temperature range: -40 to +85 °C
Applications
- clock/data distribution
- redundant clocking
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 5.1006 | $ 5.10 |
| 10+ | $ 4.3824 | $ 43.82 |
| 30+ | $ 3.9551 | $ 118.65 |
| 100+ | $ 3.5229 | $ 352.29 |
| 490+ | $ 3.323 | $ 1628.27 |
| 980+ | $ 3.2336 | $ 3168.93 |
Standard Packaging490/Full Tray | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers | |
| Manufacturer | SILICON LABS | |
| Packaging | QFN-16-EP(3x3) | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 1.8V;2.5V;3.3V | |
| Features | Output enable/shutdown;Internal termination and bias network | |
| Number of Inputs | 2 | |
| Output Frequency(Max) | 1.25GHz | |
| Number of outputs | 4 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers | |
| Manufacturer | SILICON LABS | |
| Packaging | QFN-16-EP(3x3) | |
| Operating Temperature | -40℃~+85℃ | |
| Voltage - Supply | 1.8V;2.5V;3.3V |
| Type | Description | |
|---|---|---|
| Features | Output enable/shutdown;Internal termination and bias network | |
| Number of Inputs | 2 | |
| Output Frequency(Max) | 1.25GHz | |
| Number of outputs | 4 |
Introduction
The Si53340-45 family of LVDS fanout buffers is ideal for clock/data distribution and redundant clocking applications. These devices feature typical ultra-low jitter of 50 fs and operate over a wide frequency range from dc to 1250 MHz. Built-in LDOs deliver high PSRR performance and reduces the need for external components simplifying low jitter clock distribution in noisy environments. They are available in multiple configurations and offer a selectable input clock using a 2:1 input mux. Other features include independent output enable and built-in format translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance.
Features
- Ultra-low additive jitter: 50 fs rms
- Built-in LDOs for high PSRR performance
- Up to 10 LVDS Outputs
- Any-format Inputs (LVPECL, Low-Power LVPECL, LVDS, CML, HCSL, LVCMOS)
- Wide frequency range: dc to 1250 MHz
- Output Enable option
- Multiple configuration options
- 2:1 Input Mux
- RoHS compliant, Pb-free
- Temperature range: -40 to +85 °C
Applications
- clock/data distribution
- redundant clocking
C1520073 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
Alternative Parts
| MPN | Manufacturer | Alternative Type | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|---|
| SI53340-B-GMR | SILICON LABS | Alt. Packaging | QFN-16-EP(3x3) | 98 | $ 5.9653 |