ISSI IS43LD16320A-25BLI

The IS43/46LD16320A/32160A is 512Mbit CMOS LPDDR2 DRAM. The device is organized as 4 banks of 8Meg words of 16bits or 4Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4n bits prefetched to achieve very high bandwidth.

LPDDR2-S4 is a high-speed SDRAM device internally configured as an 4-Bank memory. This device contains 536,870,912 bits (512 Megabit)

All LPDDR2 devices use a double data rate archiecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 10-bit CA bus contains command, address, and Bank/Row Buffer information. Each command uses one clock cycle, during which command information is transferred on both the positive and negative edge of the clock.

This LPDDR2-S4 device also uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially a 4n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the memory device effectively consists of a single 4n-bit wide, one clock cycle data transfer at the internal SDRAM core and four corresponding nbit wide, one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the LPDDR2 are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

Accesses begin with the registration of an Activate command, which is then followed by a Read or Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the Bank to be accessed. The address bits registered coincident with the Read or Write command are used to select the Bank and the starting column location for the burst access.

• Low-voltage Core and I/O Power Supplies VDD2 = 1.14–1.30V, VDDCA/VDDQ = 1.14 - 1.30V, VDD1 = 1.70 - 1.95V High Speed Un-terminated Logic(HSUL_12) I/O Interface
• Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O)
• Four-bit Pre-fetch DDR Architecture
• Multiplexed, double data rate, command/address inputs
• Four internal banks for concurrent operation
• Bidirectional/differential data strobe per byte of data (DQS/DQS#)
• Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16)
• ZQ Calibration
• On-chip temperature sensor to control self refresh rate
• Partial –array self refresh(PASR)
• Deep power-down mode(DPD)
• Operation Temperature Commercial TC = 0℃ to 85℃ ) Industrial TC = -40℃ to 85℃ ) Automotive, A1 ( TC = -40℃ to 85℃ ) Automotive, A2 ( TC = -40℃ to 105℃ )