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MICROCHIP DSPIC33CH512MP506-E/PT

Producent
MICROCHIP
Nr części prod.
DSPIC33CH512MP506-E/PT
Nr LCSC
C1338439
Opak.
TQFP-64(10x10)
Numer Klienta
Klucz. cechy
TQFP-64(10x10) Microcontrollers RoHS
Karta KatalogowaMICROCHIP DSPIC33CH512MP506-E/PT
Zgodność z RoHS2 dokumentów dostępnych
Gwarancja na każde zamówienie
100% Oryginalne · Zwrot lub Wymiana w ciągu 30 Dni

Specyfikacje Produktu

Wszystko
TypOpis
KategoriaIntegrated Circuits (ICs)/Embedded/Microcontrollers
ProducentMICROCHIP
Opak.TQFP-64(10x10)
Operating Temperature-40℃~+125℃
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Funkcje

Tłumaczenie AI
  • Master/Slave Core Operation
  • Independent Peripherals for Master Core and Slave Core
  • Configurable Shared Resources for Master Core and Slave Core
  • Master Core with 256 - 512 Kbytes of Program Flash with ECC and 32 - 48K Data RAM with BIST
  • Slave Core with 72 Kbytes of Program RAM (PRAM) with ECC and 16K Data RAM with BIST
  • Fast 6 - Cycle Divide
  • Live Update
  • Message Boxes and FIFO to Communicate Between Master and Slave (MSI)
  • Code Efficient (C and Assembly) Architecture
  • 40 - Bit Wide Accumulators
  • Single - Cycle (MAC/MPY) with Dual Data Fetch
  • Single - Cycle, Mixed - Sign MUL Plus Hardware Divide
  • 32 - Bit Multiply Support
  • Five Sets of Interrupt Context Selected Registers per Core for Fast Interrupt Response
  • Zero Overhead Looping
  • Internal Oscillator
  • Programmable PLLs and Oscillator Clock Sources
  • Master Core Reference Clock Output
  • Slave Core Reference Clock Output
  • Fail - Safe Clock Monitor (FSCM)
  • Fast Wake - up and Start - up
  • Backup Internal Oscillator
  • LPRC Oscillator
  • Low - Power Management Modes (Sleep, Idle, Doze)
  • Integrated Power - on Reset and Brown - out Reset
  • Up to 12 PWM Channels: 4 channels for Master Core, 8 channels for Slave Core
  • 250 ps PWM Resolution
  • 2 General Purpose 16 - Bit Timers: 1 each for Master and Slave cores
  • Peripheral Trigger Generator (PTG) Module: 1 module for Master core, Slave can interrupt on select PTG sources, Useful for automating complex sequences
  • 12 SCCP Modules: 8 modules for Master core, 4 modules for Slave core, Timer, Capture/Compare and PWM modes, 16 or 32 - bit time base, 16 or 32 - bit capture, 4 - deep capture buffer, Fully asynchronous operation, available in Sleep modes
  • 4 ADC Modules: 1 module for Master core, 3 modules for Slave core, 12 - bit, 4 Msps ADC, Up to 18 conversion channels, 250 ns conversion latency, Capacitive Voltage Divider (CVD) for touch sensing
  • 4 DAC/Analog Comparator Modules: 1 module for Master core, 3 modules for Slave core, 12 - bit DACs with hardware slope compensation, 15 ns analog comparators
  • 3 PGA Modules: 3 modules for Slave core, Can be read by Master Core ADC
  • Shared DAC/Analog Output: DAC/analog comparator outputs, PGA outputs
  • 3 UART Modules: 2 modules for Master core, 1 module for Slave core, Support for LIN/J2602 protocols and IrDA
  • Three 4 - Wire SPI/Π²S Modules: 2 modules for Master core, 1 module for Slave core
  • 2 CAN Flexible Data (FD) Modules for the Master Core
  • 3 I²C Modules: 2 modules for Master core, 1 module for Slave core, Support for SMBus
  • PPS to Allow Function Remap
  • Programmable Cyclic Redundancy Check (CRC) for the Master
  • 2 SENT Modules for Master Core
  • 8 DMA Channels: 6 channels for Master core, 2 channels for Slave core
  • In - Circuit and In - Application Programming
  • Simultaneous Debugging Support for Master and Slave
  • Master Only Debug and Slave Only Debug Support
  • Master with 3 Complex, 5 Simple Breakpoints and Slave with 1 Complex, 2 Simple Breakpoints
  • IEEE 1149.2 Compatible (JTAG) Boundary Scan
  • Trace Buffer and Run - Time Watch
  • DMT (Deadman Timer)
  • ECC (Error Correcting Code)
  • WDT (Watchdog Timer)
  • CodeGuard Security with Flash PED (Program Erase Disable)
  • CRC (Cyclic Redundancy Check)
  • RAM BIST (Built - In Self Test)

Zastosowania

Tłumaczenie AI
  • DC/DC Converters
  • AC/DC power supplies
  • Uninterruptable Power Supply (UPS)
  • Motor control: BLDC, PMSM, SR, ACIM