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TI SN74ABT16245ADGGRRoHS

Manufacturer
MPN
SN74ABT16245ADGGR
LCSC Part #
C130197
Packaging
TSSOP-48-6.2mm
Customer #
Key Attributes
16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
Datasheetpdf iconTI SN74ABT16245ADGGR
In-Stock: 69
69 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 1.8554$ 1.86
10+$ 1.5804$ 15.80
30+$ 1.4079$ 42.24
100+$ 1.1979$ 119.79
500+$ 1.1182$ 559.10
1,000+$ 1.084$ 1084.00
Standard Packaging2000/Full Reel
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Products Specifications

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TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Buffers, Drivers, Receivers, Transceivers
ManufacturerTI
PackagingTSSOP-48-6.2mm
Input type-
Voltage - Supply4.5V~5.5V
Output TypeTri-State
Current - Output High(IOH)32mA
Series74ABT
Operating Temperature-40℃~+85℃
Current - Output Low(IOL)64mA
Number of Bits per Element8
Channel TypeBidirectional
FeaturesPower-off isolation;Output enable
Number of Elements2
Propagation Delay2.2ns@5V,50pF
Quiescent Current2mA

Additional Information

TypeDetails
Minimum1
Multiple1
Standard Packaging2000
Sales UnitPiece

Introduction

AI Translation

The 'ABT16245A devices are 16-bit noninverting 3-state transceivers designed for synchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. These devices can be used as two 8-bit transceviers or one 16-bit transceiver. They allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Features

AI Translation
  • Members of the Texas Instruments Widebus™ Family
  • State-of-the-Art EPIC-IIB™ BiCMOS Design Significantly Reduces Power Dissipation
  • Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25℃
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Latch-Up Performance Exceeds 500 mA Per JESD 70
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Package Options Includes Plastic Thin Very Small-Outline (DGV), Shrink Small-Outline (DL), and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic (WD) Flat Package Using 25-mil Center-to-Center Spacings