Lattice LIFCL-40-8SG72I

The CrossLink-NX FPGA family is built on an advanced 28 nm FD-SOI semiconductor process, delivering exceptional low power consumption, compact packaging, and high system reliability. The family integrates hardened MIPI D-PHY, PCIe, and SGMII interfaces, along with a programmable flash configuration memory for secure boot and user applications. These features make it well suited for embedded video bridging, aggregation, and processing solutions in mobile, consumer electronics, industrial, and automotive applications. The architecture is based on a proven, low-power FPGA fabric comprising programmable logic, distributed and embedded memory, PLLs, and general-purpose I/O. Additionally, it incorporates embedded flash configuration memory for secure boot and user applications, a cryptographic engine for secure communications, an on-chip scrubbing controller for SEU mitigation, and an ADC with continuous-time comparators for system monitoring.

• Low-power, small-form-factor FPGA architecture based on 28 nm FD-SOI process
• High reliability with SEU-immune configuration memory and on-chip scrubbing controller for user memory
• Hard-core MIPI D-PHY supporting up to 2.5 Gbps data rate per lane
• Hard-core PCIe endpoint block supporting PCIe Gen1 (2.5 Gbps) and Gen2 (5 Gbps)
• Hard-core SGMII receiver supporting 1.25 Gbps data rate
• Embedded flash configuration memory for secure boot and user applications
• Cryptographic engine for secure communications supporting AES-256, SHA-256, and ECDSA
• On-chip 10-bit ADC and continuous-time comparator for system monitoring
• Flexible sysI/O buffers supporting multiple I/O standards
• sysCLOCK PLL for clock management
• sysDSP blocks for DSP function implementation
• sysMEM embedded memory blocks for memory function implementation
• Density migration support
• IEEE 1149.1 boundary scan support
• Hot-plug support
• On-chip programmable termination support
• User I²C IP support
• Trace ID support