Nexperia 74LVC16244ADGG,118

The 74LVC16244A; 74LVCH16244A is a 16-bit buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. The 74LVCH16244A bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

• Wide supply voltage range from 1.2 V to 3.6 V
• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• IOFF circuitry provides partial Power-down mode operation
• CMOS low power consumption
• Multibyte flow-through standard pin-out architecture
• Low inductance multiple power and ground pins for minimum noise and ground bounce
• Direct interface with TTL levels
• High-impedance when VCC = 0 V
• All data inputs have bus hold. (74LVCH16244A only)
• Complies with JEDEC standard:
  • JESD8-7A (1.65 V to 1.95 V)
  • JESD8-5A (2.3 V to 2.7 V)
  • JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
  • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

• Level translator for mixed 3.3V and 5V environments
• Direct TTL-level interface
• Partial power-down mode operation
• Low-power CMOS
• Multi-byte flow standard pin layout architecture
• Low-inductance multiple power and ground pins for minimal noise and ground bounce
• Bus hold for unused inputs