RENESAS 71V3578YS133PF

The IDT71V3576/78 are high-speed SRAMs organized as 128K x 36/256K x 18. These SRAMs contain write, data, address, and control registers. The internal logic allows the SRAMs to generate self-timed write operations based on a decision that can be deferred until the end of the write cycle. These SRAMs are fabricated using high-performance CMOS process technology and are packaged in JEDEC-standard 14mm x 20mm 100-pin TQFP, 119-ball BGA, and 165-ball FBGA packages.

• Supports 128K x 36 and 256K x 18 memory configurations.
• High system speed support.
• LBO input selects interleaved or linear burst mode.
• Self-timed write cycle with global write control, byte write enable, and byte write.
• Core supply voltage: 3.3V.
• Power-down mode controlled via ZZ input.
• I/O voltage: 3.3V.
• Optional boundary scan JTAG interface, compliant with IEEE 1149.1.
• Multiple package options available.