TI CD74HCT161EX

RCA - The CD54/74HC/HCT160, 161, 162, and 163 devices are presettable synchronous counters with look-ahead carry logic, suitable for high-speed counting applications. The CD54/74HC/HCT160 and 161 are asynchronous reset decimal and binary counters, respectively; the CD54/74HC/HCT162 and 163 are decimal and binary counters, respectively, with synchronous reset. Counting and parallel preset are both synchronously performed on the negative-to-positive transition of the clock. When the synchronous parallel enable input SPE is LOW, counting is disabled and data present at inputs P0 through P3 is loaded into the counter (provided the setup and hold requirements for SPE are met). All counters are reset when the master reset input MR is LOW. For the CD54/74HC/HCT162 and 163 counters (synchronous reset type), setup and hold time requirements relative to the clock must be satisfied. Each counter provides two count enable inputs, PE and TE, for n-bit cascading. In all counters, the reset action occurs regardless of the levels of the SPE, PE, and TE inputs (and the clock input CP in the CD54/74HC/HCT160 and 161 types). If a decimal counter is preset to an illegal state or enters an illegal state at power-up, it will return to the normal sequence within one count cycle. The look-ahead carry feature simplifies serial cascading of counters. Both count enable inputs (PE and TE) must be HIGH for counting to occur. The TE input is gated with the Q outputs of all four stages so that at maximum count, the terminal count (TC) output goes HIGH for one clock period. This TC pulse is used to enable the next cascaded stage. The CD54HC160 through 163 and CD54HCT160 through 163 are available in 16-pin hermetic dual-in-line ceramic packages (F suffix). The CD74HC160 through 163 and CD74HCT160 through 163 are available in 16-pin DIP plastic packages (E suffix) and 16-pin surface-mount plastic packages (M suffix). All types are also available in die form (H suffix).

• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Asynchronous reset (CD54/74HC/HCT160, 161)
• Synchronous reset (CD54/74HC/HCT162, 163)
• Ripple carry for high-speed counting
• Fanout (full temperature range): standard outputs — 10 LSTTL loads; bus driver outputs — 15 LSTTL loads
• Wide operating temperature range: CD74HC/HCT: -40°C to +85°C
• Balanced propagation delay and transition times
• Significantly reduced power consumption compared to LSTTL logic ICs
• Alternate source: Philips/Signetics
• CD54HC/CD74HC types: 2 to 6V operation; high noise immunity: NIL = 30%VCC, NIH = 30%VCC at VCC = 5V
• CD54HCT/CD74HCT types: 4.5 to 5.5V operation; directly compatible with LSTTL input logic, VIL max 0.8V, VIH min 2V; CMOS input compatibility: I1 ≤ 1μA at VOL, VOH