Rochester Electronics SN74S113N

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, mode control, and two clock inputs. The registers have three operating modes:

• Parallel (broadside) load
• Right shift (QA toward QD)
• Left shift (QD toward QA)

Parallel loading is accomplished by applying 4-bit data and taking the mode control input high. Data is loaded into the associated flip-flops and appears at the outputs following the high-to-low transition of Clock 2. Serial data entry is inhibited during loading.

Right shifting is accomplished on the high-to-low transition of Clock 1 with mode control low. Serial data for the right-shift mode is entered at the J-K inputs. These inputs allow the first stage to operate as a J-K, D-type, or T-type flip-flop as shown in the function table. Left shifting is accomplished on the high-to-low transition of Clock 2 with mode control high by connecting the output of each flip-flop to the parallel input of the preceding flip-flop (QD connected to input C, etc.). Serial data for this mode is entered at the D input. If both modes are to be clocked from the same source, the clock inputs may be tied together to Clock 1 and Clock 2 simultaneously. Changes to the mode control input should generally be made when both clock inputs are low; however, the conditions described in the last three lines of the function table will also ensure that register contents are protected.