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MICROCHIP A3P060-CSG121

Producent
MICROCHIP
Nr części prod.
A3P060-CSG121
Nr LCSC
C3277422
Opak.
CSP-121
Numer Klienta
Klucz. cechy
96 CSP-121 FPGAs (Field Programmable Gate Array)
Karta KatalogowaMICROCHIP A3P060-CSG121
Gwarancja na każde zamówienie
100% Oryginalne · Zwrot lub Wymiana w ciągu 30 Dni
Brak w magazynie
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Minimum: 1Wielokrotność: 1Jednostka sprzedaży: Piece
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Szt.Cena jedn.(Tylko do wglądu)Suma całkowita
1+$ 6.9774$ 6.98
200+$ 2.7003$ 540.06
500+$ 2.6061$ 1303.05
1,000+$ 2.5583$ 2558.30
Standardowa Obudowa1/Full Bag
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Specyfikacje Produktu

Wszystko
TypOpis
KategoriaIntegrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array)
ProducentMICROCHIP
Opak.CSP-121
Total RAM capacity18432bit
Number of I/O96
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Funkcje

Tłumaczenie AI
  • High density: 15K to 1M system gates, up to 144Kbit true dual-port SRAM, up to 300 user I/Os
  • Reprogrammable flash technology: 130nm, 7-layer metal (6-layer copper), flash-based CMOS process; instant power-on; single-chip solution; retains programmed design after power loss
  • High performance: 350MHz system performance; supports 3.3V, 66MHz 64-bit PCI
  • In-system programming and security: in-system programming via JTAG (IEEE 1532 compliant); FlashLock technology for FPGA content security
  • Low power: low-power core voltage; supports 1.5V-only systems; low-impedance flash switches
  • High-performance routing hierarchy: segmented, hierarchical routing and clock architecture
  • Advanced I/O: up to 700Mbps DDR, LVDS-compatible I/Os (A3P250 and above); mixed-voltage operation at 1.5V, 1.8V, 2.5V, and 3.3V; wide-range supply voltage per JESD8-B, allowing I/O operation from 2.7V to 3.6V; I/O voltage selection by bank — up to 4 banks per device; single-ended I/O standards: LVTTL, LVCMOS 3.3V/2.5V/1.8V/1.5V, 3.3V PCI/PCI-X, and LVCMOS 2.5V/5.0V input; differential I/O standards: LVPECL, LVDS, BLVDS, and MLVDS (A3P250 and above); I/O registers on input, output, and enable paths; hot-swap and cold-sparing I/O support; programmable output slew rate and drive strength; weak pull-up/pull-down; IEEE 1149.1 (JTAG) boundary scan support; pin-compatible packages within the ProASIC3 family
  • Clock conditioning circuits and PLL: six clock conditioning circuit blocks, one with integrated PLL; configurable phase shift, multiply/divide, delay capability, and external feedback; wide input frequency range (1.5MHz to 350MHz)
  • Embedded memory: 1Kbit flash ROM user NVM; SRAM and FIFO with variable aspect ratio 4,608-bit RAM blocks (supports ×1, ×2, ×4, ×9, and ×18 configurations); true dual-port SRAM (except ×18 configuration)
  • ARM processor support: M1 ProASIC3 devices — ARM Cortex-M1 soft-core processor with or without debug capability