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MICROCHIP PIC18F16Q41-E/P

Produttore
Cod. Prod.
PIC18F16Q41-E/P
Cod. LCSC
C3231733
Imballo
PDIP-20
Numero Cliente
Attr. chiave
PIC 8 Bit 64MHz PDIP-20 Microcontrollers RoHS
Scheda TecnicaMICROCHIP PIC18F16Q41-E/P
Conformità RoHS2 documenti disponibili
Parti alternative2
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Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Embedded/Microcontrollers
ProduttoreMICROCHIP
ImballoPDIP-20
DAC (Bit)8bit
ADC (Bit)12bit
Number of I/O18
Operating Temperature-40℃~+125℃
Program Memory TypeFLASH
Voltage - Supply1.8V~5.5V
EEPROM512Byte
Program Storage Size64KB
CPU CorePIC
Core Size8 Bit
CPU Maximum Speed64MHz
Oscillator TypeBuilt-in

Descrizione

Traduzione AI

The PIC18-Q41 microcontroller family is available in 14/20-pin devices for sensor and real-time control applications. This analog-focused family features a 12-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced capacitive touch sensing, averaging, filtering, oversampling and threshold comparison, two 8-bit DAC modules and an Operational Amplifier. The family showcases a 16-bit PWM module that provides dual independent outputs on the same time base. Additional features include vectored interrupt controller with fixed latency for handling interrupts, system bus arbiter, Direct Memory Access (DMA) capabilities, UART with support for asynchronous, DMX, DALI and LIN protocols, SPI, I2C, and a programmable 32-bit CRC with Memory Scan. This family also includes memory features such as Memory Access Partition (MAP) to support users in data protection and bootloader applications, as well as Device Information Area (DIA) that stores factory calibration values to help improve temperature sensor accuracy.

Caratteristiche

Traduzione AI
  • C Compiler Optimized RISC Architecture
  • Operating Speed:
    • DC – 64 MHz clock input
    • 62.5 ns minimum instruction cycle
  • Four Direct Memory Access (DMA) Controllers:
    • Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM, or SFR/GPR spaces
    • User-programmable source and destination sizes
    • Hardware and software triggered data transfers
  • Vectored Interrupt Capability:
    • Selectable high/low priority
    • Fixed interrupt latency of three instruction cycles
    • Programmable vector table base address
    • Backwards compatible with previous interrupt capabilities
  • 128-Level Deep Hardware Stack
  • Low-Current Power-on Reset (POR)
  • Configurable Power-up Timer (PWRT)
  • Brown-out Reset (BOR)
  • Low-Power BOR (LPBOR) Option
  • Windowed Watchdog Timer (WWDT):
    • Watchdog Reset on too long or too short interval between watchdog clear events
    • Variable prescaler selection
    • Variable window size selection