RENESAS R5F104GLANA#40

This platform is a true low-power platform for general-purpose applications, with active current consumption as low as 66 µA/MHz, and only 0.60 µA when running only the real-time clock and low-voltage detector. It operates across a voltage range of 1.6 V to 5.5 V, with code flash capacities from 16 KB to 512 KB, and delivers up to 44 DMIPS performance at 32 MHz.

• Ultra-low power technology: Single supply voltage VDD from 1.6 V to 5.5 V, supporting 1.8 V device low-voltage operation; HALT mode, STOP mode, and SNOOZE mode supported.
• RL78 CPU core: CISC architecture with 3-stage pipeline; minimum instruction execution time adjustable from high-speed (0.03125 µs @ 32 MHz high-speed on-chip oscillator) to ultra-low-speed (30.5 µs @ 32.768 kHz subsystem clock); multiply/divide/multiply-accumulate instructions supported; 1 MB address space; general-purpose registers: (8-bit registers × 8) × 4 banks; on-chip RAM: 2.5 KB to 48 KB.
• Code flash: 16 KB to 512 KB capacity; 1 KB block size; block erase and rewrite inhibit supported (security function); on-chip debugging supported; self-programming with boot swap and flash protection window supported.
• Data flash: 4 KB and 8 KB capacity; background operation supported, allowing instruction execution from program memory during data flash rewrite; typical endurance: 1,000,000 rewrite cycles; rewrite voltage VDD: 1.8 V to 5.5 V.
• High-speed on-chip oscillator: Selectable frequencies: 64 MHz, 48 MHz, 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz; high accuracy ±1.0% (VDD = 1.8 V to 5.5 V, TA = -20°C to +85°C).
• Operating ambient temperature: TA = -40°C to +85°C (A: consumer applications, D: industrial applications); TA = -40°C to +105°C (G: industrial applications).
• Power management and reset: On-chip power-on reset circuit; on-chip voltage detector (selectable interrupt and reset from 14 levels).
• Data transfer controller: Transfer modes include normal transfer, repeat transfer, and block transfer; activated by interrupt sources; chained transfer supported.
• Event link controller: Links 19 to 26 types of event signals to designated peripheral functions.
• Serial interfaces: Simplified SPI (CSI): 3 to 8 channels; UART/UART (LIN bus supported): 3 or 4 channels; I²C/simplified I²C: 4 to 10 channels.
• Timers: 16-bit timers: 8 to 12 channels (Timer Array Unit: 4 to 8 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel); 12-bit interval timer: 1 channel; real-time clock: 1 channel (99-year calendar, alarm function, and clock correction supported); watchdog timer: 1 channel (operable with dedicated low-speed on-chip oscillator).
• A/D converter: 8/10-bit resolution ADC (VDD = 1.6 V to 5.5 V); analog inputs: 8 to 20 channels; internal reference voltage (1.45 V) and temperature sensor included.
• D/A converter: 8-bit resolution DAC (VDD = 1.6 V to 5.5 V); analog outputs: none or up to 2 channels; output voltage range: 0 V to VDD; real-time output supported.
• Comparators: None or up to 2 channels; operating modes: comparator high-speed mode, comparator low-speed mode, and window mode; reference voltage selectable from external or internal source.
• I/O ports: 26 to 92 I/O ports (N-channel open-drain I/O with 6 V tolerance: 2 to 4; N-channel open-drain I/O with VDD/EVDD tolerance: 10 to 28); configurable as N-channel open-drain, TTL input buffer, and on-chip pull-up resistor; multi-voltage interface supporting 1.8 V/2.5 V/3 V devices; on-chip key interrupt; on-chip clock output/buzzer output controller.
• Other: On-chip BCD correction circuit.