Infineon/CYPRESS CY7C1021B-12ZC

This device is a high-performance CMOS SRAM with a capacity of 1 megabit, organized as 65,536 words × 16 bits. It features an automatic power-down function that significantly reduces power consumption when the device is deselected. Write operations are performed by asserting Chip Enable (CE) and Write Enable (WE) low. When Byte Low Enable (BLE) is low, data is written from the I/O pins (I/O1 to I/O8) to the location specified by the address pins (A0 to A15). When Byte High Enable (BHE) is low, data is written from the I/O pins (I/O9 to I/O16). Read operations are performed by asserting Chip Enable (CE) and Output Enable (OE) low while Write Enable (WE) is high. When BLE is low, data from the memory cell specified by the address pins appears on I/O1 to I/O8. When BHE is low, data appears on I/O9 to I/O16. The I/O pins (I/O1 to I/O16) are in a high-impedance state when the device is deselected, the output is disabled, BHE and BLE are disabled, or during a write operation. The device is available in standard 44-pin TSOP Type II and 44-pin 400-mil wide SOJ packages.

• Multiple temperature ranges: commercial (0℃ to 70℃), industrial (-40℃ to 85℃), automotive (-40℃ to 125℃)
• High-speed access: tAA = 12 ns (commercial and industrial), tAA = 15 ns (automotive)
• CMOS process for optimized speed and power consumption
• Low active power dissipation, 770 mW maximum
• Automatic power-down when deselected
• Independent upper and lower byte control
• Available in lead-free and non-lead-free 44-pin TSOP II and 44-pin 400-mil wide SOJ packages