Infineon/CYPRESS CY7C1460AV33-200AXCKG

CY7C1460AV33/CY7C1462AV33 are 3.3V, 1M×36 / 2M×18 synchronous pipelined burst SRAMs with No Bus Latency (NoBL™) logic. They are designed to support unlimited true back-to-back read and write operations with no wait states. The CY7C1460AV33/CY7C1462AV33 feature advanced NoBL logic that enables continuous read and write operations with data transfer on every clock cycle. This significantly improves data throughput in systems requiring frequent write-to-read transitions. The CY7C1460AV33/CY7C1462AV33 are pin-compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal; when deasserted, operation is suspended and the previous clock cycle is extended. Write operations are controlled by the Byte Write Select (BW̅a–BW̅d for CY7C1460AV33 and BW̅a–BW̅b for CY7C1462AV33) and Write Enable (WE) inputs. All write operations are performed through an on-chip synchronous self-timed write circuit. Three synchronous chip selects (CE̅1, CE2, CE̅3) and one asynchronous output enable (OE) facilitate memory bank selection and output three-state control. To prevent bus contention, the output drivers synchronously enter three-state during the data portion of a write sequence.

• Pin-compatible with ZBT, functionally equivalent
• Supports 250 MHz bus operation, zero wait states
• Available speed grades: 250, 200, and 167 MHz
• Internal self-timed output buffer control, no asynchronous OE required
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• 3.3 V supply voltage
• 3.3 V/2.5 V I/O supply voltage
• Fast clock-to-output time of 2.6 ns (for 250 MHz devices)
• Clock Enable (CEN) pin for operation pause
• Synchronous self-timed write operation
• CY7C1460AV33 available in JEDEC standard lead-free 100-pin TQFP and non-lead-free 165-ball FBGA packages; CY7C1462AV33 available in JEDEC standard lead-free 100-pin TQFP package
• IEEE 1149.1 JTAG boundary scan compliant
• Burst capability supporting linear or interleaved burst order
• "ZZ" sleep mode option and stop clock option available