micron MT48LC64M8A2TG-75 IT:C

512Mb SDRAM is a high-speed CMOS dynamic random access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the rising edge of the clock signal CLK). Each 134,217,728-bit bank in the x4 configuration is organized as 8192 rows × 4096 columns × 4 bits. Each 134,217,728-bit bank in the x8 configuration is organized as 8192 rows × 2048 columns × 8 bits. Each 134,217,728-bit bank in the x16 configuration is organized as 8192 rows × 1024 columns × 16 bits. Read and write accesses to the SDRAM are burst-oriented; access begins at a selected location and continues for a programmed number of locations in a programmed sequence. Access begins with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] selects the bank; A[12:0] selects the row). The address bits registered coincident with the READ or WRITE command are used to select the starting address.

• Compliant with PC100 and PC133 standards
• Fully synchronous; all signals registered on the rising edge of the system clock
• Internal pipelined operation; column address can change every clock cycle
• Internal banks for hidden row access/precharge
• Programmable burst length: 1, 2, 4, 8, or full page
• Auto precharge, including concurrent auto precharge and auto refresh modes
• Self-refresh mode
• Auto refresh
• 64ms, 8192-cycle refresh (commercial and industrial grade)
• LVTTL-compatible inputs and outputs
• Single 3.3V ± 0.3V power supply