AMD/XILINX XC2C384-10FT256C

The CoolRunner-II 384 macrocell device is designed for high-performance and low-power applications. This not only saves power for high-end communication devices but also provides high speed for battery-powered devices. Thanks to its low-power standby and dynamic operation characteristics, the overall system reliability is improved. Multiple package options are available:

• 144-pin TQFP, 118 user I/Os
• 208-pin PQFP, 173 user I/Os
• 256-ball FT (1.0mm) BGA, 212 user I/Os
• 324-ball FG (1.0mm) BGA, 240 user I/Os All packages are available in lead-free versions.

• Fastest 1.8V in-system programming (ISP) via IEEE 1532 (JTAG) interface
• IEEE 1149.1 JTAG boundary scan test
• Optional Schmitt trigger input (per pin)
• Unmatched low-power management, DataGATE Enable (DGE) signal controlled
• Four independent I/O banks
• RealDigital 100% CMOS product term generation
• Flexible clock modes, optional dual-edge triggered registers, clock divider (÷2, ÷4, ÷6, ÷8, ÷10, ÷12, ÷14, ÷16) CoolCLOCK
• Global signal options with macrocell control: multiple global clocks with per-macrocell phase selection, multiple global output enables, global set/reset
• Advanced design security
• PLA architecture, superior pin assignment retention, 100% product term routability between function blocks
• Open-drain output option for wire-OR and LED driving
• Optional bus hold, tri-state, or weak pull-up on selected I/O pins
• Optional ground configuration on unused I/Os
• Mixed I/O voltages, compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels; SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
• Hot-swap capable
• Dual-edge triggered flip-flop functionality available per macrocell
• Includes circuitry for eight different division selections of one externally supplied global clock (GCK2)
• DataGATE selectively disables irrelevant CPLD inputs at specified time points
• I/O banking: four I/O banks on CoolRunner-II 384-macrocell devices for easy interfacing with 3.3V, 2.5V, 1.8V, and 1.5V devices
• CoolRunner-II 384-macrocell CPLD compatible with various I/O standards
• Xilinx CoolRunner-II CPLD fabricated using 0.18-micron process technology derived from leading-edge FPGA product development
• CoolRunner-II CPLD employs RealDigital design technology, using CMOS technology in both manufacturing and design methodology
• RealDigital design technology implements sum-of-products using cascaded CMOS gates rather than conventional sense-amplifier approaches
• CoolRunner-II 384-macrocell supports LVCMOS, LVTTL, SSTL, and HSTL I/O implementations
• CoolRunner-II CPLD also compatible with 1.5V I/O when using Schmitt trigger inputs
• 16-bit up/down resettable binary counter (one counter per function block)