NXP LPC43S67JET256E

The LPC43S6x is an ARM Cortex-M4-based microcontroller for embedded applications, featuring an ARM Cortex-M0 coprocessor and an ARM Cortex-M0 subsystem for peripheral management, up to 1 MB flash memory, 154 kB on-chip SRAM, 16 kB EEPROM, a quad-channel SPI flash interface (SPIFI), advanced configurable peripherals such as SCTimerPWM and a Serial GPIO (SGPIO) interface, security features with an AES engine, two high-speed USB controllers, Ethernet, an LCD controller, an external memory controller, and multiple digital and analog peripherals. The LPC43S6x CPU operates at up to 204 MHz. The ARM Cortex-M4 is a 32-bit core offering system enhancements including low power consumption, enhanced debug features, and a high level of support block integration. The ARM Cortex-M4 CPU employs a 3-stage pipeline with a Harvard architecture, featuring separate local instruction and data buses plus a third bus for peripherals, and incorporates a prefetch unit with branch prediction. The ARM Cortex-M4 supports single-cycle DSP and SIMD instructions, with an integrated hardware floating-point unit. The LPC43S6x includes an application-level ARM Cortex-M0 coprocessor and a second ARM Cortex-M0 subsystem dedicated to managing SGPIO and SPI peripherals. The ARM Cortex-M0 coprocessor is an energy-efficient, easy-to-use 32-bit core that is upward code- and tool-compatible with the Cortex-M4 core. Positioned as a replacement for existing 8/16-bit microcontrollers, the Cortex-M0 coprocessor delivers up to 204 MHz performance with a simple instruction set and reduced code size. The Cortex-M0 coprocessor hardware multiplier is implemented as a 32-cycle iterative multiplier.

• ARM Cortex-M4 processor (revision r0p1), up to 204 MHz
• Built-in MPU with 8 regions
• Built-in NVIC
• Hardware floating-point unit
• NMI input
• JTAG and SWD, serial trace, 8 breakpoints, 4 watchpoints
• ETM and ETB support
• SysTick timer
• ARM Cortex-M0 co-processor (revision r0p0), offloads the main ARM Cortex-M4 application processor
• Up to 204 MHz
• JTAG support
• Built-in NVIC
• ARM Cortex-M0 co-processor controls SPI and SGPIO on a separate AHB multi-layer matrix, with 2 kB + 16 kB SRAM
• Up to 204 MHz
• Connected to the main AHB multi-layer matrix and main ARM Cortex-M4 processor via inter-processor bridge
• JTAG support, built-in NVIC
• Up to 1 MB on-chip dual-bank flash with flash accelerator
• 16 kB on-chip EEPROM data memory
• 154 kB SRAM for code and data
• Multiple SRAM blocks with independent bus access; two SRAM blocks can be powered down individually
• 64-bit OTP memory for general-purpose use
• Two banks (256 bits total) OTP memory for AES key storage; one bank supports encrypted key storage for boot image decryption
• AES engine with DMA support for boot image and data encryption/decryption; programmable via ROM-based API
• SGPIO interface
• SCTimer/PWM subsystem on AHB bus
• GIMA for cross-connecting multiple I/Os to event-driven peripherals such as timers, SCTimer/PWM, ADC0/1
• 4-lane SPIFI, up to 52 MB/s transfer rate
• 10/100T Ethernet MAC with RMII and MII interface, DMA support for high throughput at low CPU load, IEEE 1588 timestamping/advanced timestamping (IEEE 1588-2008 v2)
• One high-speed USB 2.0 host/device/OTG interface with DMA support and on-chip high-speed PHY
• One high-speed USB 2.0 host/device interface with DMA support, on-chip full-speed PHY, and ULPI interface for external high-speed PHY
• USB electrical test software included in ROM USB stack
• One 550 UART with DMA support and full modem interface
• Three 550 USARTs with DMA and synchronous mode support, ISO7816-compliant smart card interface; one USART with IrDA interface
• Up to two C_CAN 2.0B controllers, one channel each
• Two SSP controllers with FIFO and multi-protocol support, both with DMA support
• One SPI controller
• One Fast-mode Plus I2C bus interface with monitor mode; open-drain I/O pins compliant with full I2C bus specification, up to 1 Mbit/s
• One standard I2C bus interface with monitor mode; standard I/O pins
• Two I2S interfaces, each with DMA support, one input and one output each
• EMC supporting external SRAM, ROM, NOR flash, and SDRAM devices
• LCD controller with DMA support; programmable resolution up to 1024H×768V; supports mono and color STN panels and TFT color panels; supports 1/2/4/8 bpp CLUT and 16/24-bit direct color
• SD/MMC card interface

• Embedded applications