MICROCHIP PIC32CX2051MTSH128-I/X9B

The PIC32CXMTSH series is a family of system-on-chip solutions for residential single-phase and two-phase metering applications, achieving Class 0.2 metering accuracy over a 3000:1 dynamic range across the industrial temperature range, compliant with ANSI C12.20-2002 and IEC 62053-22 standards. These metrology-enabled microcontrollers deliver unprecedented integration and flexibility around dual 32-bit Arm Cortex-M4F RISC processors, allowing application, communication, and metrology functions to be integrated in a single device. The application core runs at up to 200 MHz and the metrology core at up to 240 MHz, with up to 2 MB of embedded Flash, up to 560 KB of SRAM, and 16 KB instruction and 8 KB data cache/tightly coupled memory integrated on-chip. A QSPI interface supporting execute-in-place with coupled on-the-fly AES128 encryption future-proofs the device and ensures platform scalability when expanded memory or evolving system requirements arise. The family is designed to meet international metrology standards with a clear separation between application/communication and metrology functions. Each core is equipped with an embedded memory protection unit and high-speed bus matrix to protect legally relevant code from core and peripheral access. Secure boot and secure key storage, combined with advanced cryptographic/hash hardware accelerators — including ECC, RSA, AES128/256, and SHA256/512 — support diverse encryption and authentication protocols. The peripheral set includes metrology-dedicated precision voltage references and up to five simultaneously sampled Delta-Sigma ADC subsystems, supporting measurement of two voltages, two currents, and one temperature sensor. The family also features a segment LCD controller, tamper detection, floating-point unit, memory protection unit, FLEXCOM peripherals supporting I2C, SPI, and UART/USART interfaces, three PWMs for pulse output functions, 12-channel general-purpose 32-bit timers, a 12-bit ADC, analog comparators, and a battery-backed RTC with operating current as low as 1 μA. PIC32CXMTSH devices are available in an EP-TQFP 128-pin exposed-pad package.

• Application/Host Core: Arm Cortex-M4F, up to 200 MHz; 16 KB ITCM/I-Cache, 8 KB DTCM/D-Cache; memory protection unit; IEEE 754-compliant single-precision FPU with DSP instructions and Thumb-2 instruction set; up to 2 MB embedded dual-plane/dual-boot Flash with built-in ECC, read-while-write support, write/erase suspend/resume, 100K write/erase cycle endurance; up to 512 KB embedded SRAM.
• Metrology/Coprocessor Core: Arm Cortex-M4F, up to 240 MHz; IEEE 754-compliant single-precision FPU, memory protection unit, DSP instructions and Thumb-2 instruction set; 32 KB embedded SRAM for program code and data; 16 KB embedded SRAM for program data.
• Symmetric/Asynchronous Dual-Core Architecture: interrupt-based inter-processor communication; asynchronous clocks; one interrupt controller per core.
• Energy Metering Analog Front End: single-phase and two-phase meter support; metering accuracy up to Class 0.2; compatible with Microchip IEC- and ANSI-compliant metering DSP library; five Delta-Sigma ADC measurement channels, 24-bit resolution, 102 dB dynamic range; current channels with pre-gain for direct connection to shunts, CTs, and Rogowski coil sensors without active components; dedicated current channel for neutral current measurement; precision voltage reference with typical temperature drift of 10 ppm/°C, software-correctable via factory-programmed calibration registers; dedicated 2.8V LDO regulator for analog front-end supply; operating voltage 3.0V to 3.6V, ultra-low power: < 2.5 mW per channel at 3.3V.
• Security and Cryptography: secure boot; secure key storage and transfer to AES and AES bridge without processor intervention; OTP block for software monotonic counter; security fuse to disable debug port access; true random number generator; deterministic random number generator supporting NIST 800-90B requirements; AES: 256-, 192-, 128-bit key algorithms, FIPS PUB-197 compliant, ARIA support; AES128 on-the-fly encryption/decryption bridge for QSPI communication; secure hash algorithms SHA1, SHA224, SHA256, SHA384, and SHA512, FIPS PUB-197 compliant with associated HMAC support; classic public-key cryptography controller supporting RSA, elliptic curve, DSA, DRNG; 768-bit general-purpose backup registers configurable as write-once; automatic immediate key zeroization upon detection of Flash erase signal; tamper detection with timestamp, configurable immediate response upon event detection; SHA256-based integrity check module, autonomous operation.
• Dual-Core Shared System Controller: power management including embedded core and LCD voltage regulators with single-supply support; power monitor; ultra-low power backup mode; clock management including programmable PLL and oscillator clock sources; clock failure detection; CPU frequency monitoring.