SKYWORKS SI5348B-E12188-GMR

The Si5348 combines the industry’s smallest footprint and lowest power network synchronizer clock with unmatched frequency synthesis flexibility and ultra-low jitter. The Si5348 is ideally suited for wireless backhaul, IP radio, small and macro cell wireless communications systems, and data center switches requiring both traditional and packe based network synchronization. The three independent DSPLLs are individually configurable as a SyncE PLL, IEEE 1588 DCO or a general-purpose PLL for processor/FPGA clocking. The Si5348 can also be used in legacy SETS systems needing Stratum 3/3E compliance. The optional digitally controlled oscillator (DCO) mode provides precise timing adjustment to 1 ppt for 1588 (PTP) clock steering applications. The unique design of the Si5348 allows the TCXO/OCXO reference input to determine the device’s frequency accuracy and stability. The Si5348 is programmable via a serial interface with in-circuit programmable non-volatile memory so it always powers up into a known configuration. Programming the Si5348 is easy with ClockBuilder Pro software. Factory pre-programmed devices are also available.

• Three independent DSPLLs in a single monolithic IC supporting flexible SyncE/ IEEE 1588 and SETS architectures
• Ultra-low jitter of 95 fs
• Enhanced hitless switching minimizes output phase transients
• Input frequency range:
  • External crystal: 48 to 54 MHz
  • REF clock: 5 to 250 MHz
  • Diff clock: 8 kHz to 750 MHz
  • LVCMOS clock: 8 kHz to 250 MHz
• Output frequency range:
  • Differential: 1 PPS to 718.5 MHz
  • LVCMOS: 1 PPS to 250 MHz
• Meets the requirements of:
  • ITU-T G.8262 (SyncE) EEC Options 1 and 2
  • ITU-T G.812 Type III, IV
  • ITU-T G.813 Option 1
  • Telcordia GR-1244, GR-253 (Stratum-3/3E)
• Independent Frequency-on-the-fly for each DSPLL
• Pin or software controllable DCO on each DSPLL with typical resolution to 1 ppt/step
• TCXO/OCXO reference input determines DSPLL free-run/holdover accuracy and stability
• Programmable jitter attenuation bandwidth per DSPLL: 0.001 Hz to 4 kHz
• Highly configurable output drivers: LVDS, LVPECL, LVCMOS, HCSL, CML
• Core voltage:
  • VDD: 1.8 ±5%
  • VDDA: 3.3 ±5%
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
• Built-in power supply filtering
• Status monitoring: LOS, OOF, LOL
• Serial Interface: I²C or SPI (3-wire or 4-wire)
• ClockBuilder Pro software simplifies device configuration
• Temperature range: -40 to +85 °C
• Pb-free, RoHS-6 compliant

• Synchronous Ethernet (SyncE) ITU-T G.8262 EEC Option 1 & 2
• Telecom Boundary Clock (T-BC) as defined by ITU-T G.8273.2
• IEEE 1588 (PTP) slave clock synchronization
• Stratum 3/3E, G.812, G.813 network synchronization