Tai-Action TAE32F5610TQC256

This series is based on the ARM Cortex-M4 core, operating at a system frequency of 160MHz, with a built-in 32-bit hardware multiply/divide accelerator and IQDIV hardware acceleration algorithm. Memory resources include a 256KB FLASH program memory and 32KB system SRAM; FLASH supports read/write/erase protection, zero-latency execution, and single/dual-bank operation. Power management supports a 3.0V~3.6V single-supply input, with power-on/power-off reset, brown-out reset, independent watchdog, and window watchdog. The clock system integrates an HSI oscillator, an LSI oscillator, supports 6MHz~26MHz crystal oscillators and crystal-less solutions, and incorporates a clock security system and temperature sensor. The DMA controller features 4 independent channels, supporting arbitrary transfers between memory and peripherals. The number of GPIO pins ranges from 22 to 66 depending on the package, with support for alternate functions, bit-band operations, internal pull-up/pull-down resistors, external interrupts, and 4-level drive strength adjustment, with a maximum drive capability of 24mA. Timer resources include 5 sets of 16-bit/32-bit general-purpose timers, supporting timing, PWM output, and capture functions. The high-resolution PWM module supports 4 pairs of 8 PWM output channels with a minimum resolution of 195ps, featuring complementary/independent outputs, symmetric/asymmetric waveforms, dead-time insertion, fault protection, and multi-channel synchronization. The ADC subsystem includes 2 independent high-speed ADCs supporting a 5MSPS sample rate, 13-bit resolution, 22 analog input channels, with regular and injected sequence conversions, gain/offset compensation, and multiple trigger modes. The DAC and comparator subsystem includes 4 sets of 12-bit DACs and 4 sets of CMPs; DAC INL/DNL is less than 5LSB with programmable waveform output; CMP propagation delay is typically 18ns. Communication interfaces include 5 UARTs, 2 SPIs, 2 I²Cs, 2 CAN controllers, and 1 QEI interface. Additional features include adjustable LVD monitoring, a 128-bit chip unique ID, sleep and stop low-power modes, and a 2-wire SWD debug interface. Devices meet the industrial junction temperature range of -40°C~150°C, ESD rating ≥ ±6KV, and are available in LQFP80, LQFP64, QFN56, QFN40, and QFN32 packages.

• ARM Cortex-M4 core, system clock frequency 160MHz
• Built-in 32-bit hardware multiply/divide accelerator and IQDIV hardware acceleration algorithm
• Built-in 256KB FLASH program memory and 32KB system SRAM
• 3.0V~3.6V single supply input, with power-on/power-off reset and brownout reset
• Built-in independent watchdog and window watchdog
• Built-in HSI high-frequency oscillator and LSI low-frequency oscillator, supports 6MHz~26MHz crystal oscillation
• Integrated clock security system, crystal anomaly detection, and temperature sensor
• Built-in 4 independent DMA channels, supports arbitrary transfers between memory and peripherals
• General-purpose I/O count varies by package, supports function multiplexing, bit manipulation, and external interrupts
• I/O drive strength 4-level adjustable, up to 24mA
• Built-in 5 sets of 16-bit/32-bit general-purpose timers, supports timing, PWM output, and capture
• High-precision PWM supports 4 pairs / 8 channels output, minimum resolution 195ps
• Built-in 2 independent high-speed ADCs, supports 5MSPS sampling rate, 13-bit resolution
• Built-in 4 sets of 12-bit DACs and 4 sets of comparators, CMP conversion delay typical 18ns
• Communication interfaces: 5× UART, 2× SPI, 2× I²C, 2× CAN, and 1× QEI
• Programmable voltage detector, 128-bit unique ID, and low-power modes
• 2-wire SWD debug interface
• Industrial junction temperature range -40°C ~ 150°C, ESD rating ≥ ±6KV