Infineon/CYPRESS CY8C4145LQI-PS423

PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. PSoC 4100PS is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity.

• Two dedicated analog-to-digital converters (ADC) including a 12-bit SAR ADC and a 10-bit single-slope ADC
• Four opamps, two low-power comparators, and a flexible 38-channel analog mux to create custom Analog Front Ends (AFE)
• Two 13-bit Voltage DACs
• Two 7-bit Current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
• Cypress's fourth-generation CapSense Sigma-Delta (CSD) providing best-in-class signal-to-noise ratio (SNR) and water tolerance
• Cypress-supplied software component makes capacitive sensing design easy
• Automatic hardware tuning (SmartSense™)
• LCD drive supported on all pins (common or segment)
• Operates in Deep-Sleep mode with four bits per pin memory
• Three independent serial communication blocks (SCBs) that are run-time configurable as I2C, SPI or UART
• Eight 16-bit timer/counter/pulse-width modulator (TCPWM) blocks with center-aligned, edge, and pseudo-random modes
• Arm Cortex-M0+ CPU up to 48 MHz
• Up to 32 KB of flash with read accelerator
• Up to 4 KB of SRAM
• Eight-channel descriptor-based DMA controller
• 1.71-V to 5.5-V operation
• Deep-Sleep mode with operational analog and 2.5-μA digital system current
• Watch Crystal Oscillator (WCO)
• Up to 38 GPIOs that can be used for analog, digital, CapSense, or LCD functions with programmable drive modes, strength and slew rates
• Includes eight Smart I/Os to implement pin-level Boolean operations on input and output signals
• 48-pin QFN, 48-pin TQFP, 28-pin SSOP, and 45-ball WLCSP packages
• Integrated Design Environment (IDE) provides schematic-capture design entry and build (with automatic routing of analog and digital signals) and concurrent firmware development with an Arm-SWD debugger
• GUI-based configurable PSoC Components with fully engineered embedded initialization, calibration and correction algorithms
• Application Programming Interfaces (API) for all fixed-function and programmable peripherals
• After schematic-capture, firmware development can be done with Arm-based industry-standard development tools