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TI ADS4225IRGCT

제조업체
제조사 품번
ADS4225IRGCT
LCSC 번호
C2862966
포장
VQFN-64-EP(9x9)
고객 번호
주요 제원
ADS42XX Dual-Channel, 14-Bit/12-Bit, 160MSPS/125MSPS/65MSPS Ultra-Low Power ADC
데이터시트TI ADS4225IRGCT
RoHS 준수2개 문서 이용 가능
대체 부품5
모든 주문 보장
100% 정품 · 30일 반품 또는 교환
품절
재입고 알림
최소값: 1배수: 1판매 단위: Piece
BOM 목록에 추가
수량단가(참고용)총액
1+$ 53.2174$ 53.22
30+$ 50.5653$ 1516.96
표준 패키지250/Full Reel
수량이 많을수록 더 좋은 가격?
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제품 사양

전체
타입설명
카테고리Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
제조업체TI
포장VQFN-64-EP(9x9)
Operating Temperature-40℃~+85℃
InterfaceParallel port
Quiescent Current (Iq)-
Voltage - Supply1.7V~1.9V
Number of Channels2
Integral non - linearity2LSB
Voltage ReferenceBuilt-in
Clock/Oscillator-
Clock Frequency125MHz
FeaturesSoft reset
Resolution(Bits)12;125MHz
S/N Ratio70.5dB
DNL (LSB)0.5LSB
ADC architecture-
Programmable GainSupport
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개요

AI 번역

The ADS424x and ADS422x series devices are low-speed variants of the ultra-low-power series of dual-channel 14-bit/12-bit analog-to-digital converters (ADCs). These devices achieve high dynamic performance through innovative design techniques and operate with a 1.8V power supply, consuming extremely low power. This topology makes the ADS424x/422x highly suitable for multi-carrier, high-bandwidth communication converters. The ADS424x/422x features fine gain options, which can be used to improve the SFDR performance within a lower full-scale output range. These devices include a DC offset correction loop to eliminate the ADC offset. Both the double data rate (DDR) LVDS and parallel CMOS digital output interfaces are available in a compact VQFN-64 package. These devices incorporate an internal reference and eliminate the traditional reference pins and associated decoupling capacitors. All devices are rated to operate within the industrial temperature range (-40°C to 85°C).

주요 특징

AI 번역
  • Ultra-low power, 1.8V single-supply, CMOS output:
    • Total power consumption of 183mW at 65MSPS
    • Total power consumption of 277mW at 125MSPS
    • Total power consumption of 332mW at 160MSPS
  • High dynamic performance:
    • SFDR of 88dBc at 170MHz
    • SNR of 71.4dBFS at 170MHz
  • Crosstalk: >90dB at 185MHz
  • Programmable gain up to 6dB for SNR/SFDR performance trade-off
  • DC offset correction
  • Output interface options:
    • 1.8V parallel CMOS interface
    • DDR LVDS with programmable swing:
      • Standard swing: 350mV
      • Low swing: 200mV
  • Input clock amplitude as low as 200mV_PP
  • Package: VQFN-64 (9.00mm x 9.00mm)

응용 분야

AI 번역
  • Wireless communication infrastructure
  • Software-defined radio
  • Power amplifier linearization

대체 부품

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