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TI CDC318ADLR product image
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TI CDC318ADLR

제조업체
제조사 품번
CDC318ADLR
LCSC 번호
C2651333
포장
SSOP-48-300mil
고객 번호
주요 제원
3.135V~3.465V 100MHz 18 SSOP-48-300mil Clock Buffers, Drivers RoHS
데이터시트TI CDC318ADLR
RoHS 준수1개 문서 이용 가능
모든 주문 보장
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제품 사양

전체
타입설명
카테고리Integrated Circuits (ICs)/Clock/Timing/Clock Buffers, Drivers
제조업체TI
포장SSOP-48-300mil
Operating Temperature0℃~+70℃
Voltage - Supply3.135V~3.465V
FeaturesMulti-channel fan-out/isolation drive;Output enable/shutdown;Internal termination and bias network
Number of Inputs1
Output Frequency(Max)100MHz
Number of outputs18
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개요

AI 번역

The CDC318A is a high-performance clock buffer designed to distribute high-speed clocks in PC applications. This device distributes one input (A) to 18 outputs (Y) with minimum skew for clock distribution. The CDC318A operates from a 3.3-V power supply. It is characterized for operation from 0°C to 70°C. This device has been designed with consideration for optimized EMI performance. Depending on the application layout, damping resistors in series to the clock outputs (like proposed in the PC100 specification) may not be needed in most cases. The device provides a standard mode (100K-bits/s) I2C serial interface for device control. The implementation is as a slave/receiver. The device address is specified in the I2C device address table. Both of the I2C inputs (SDATA and SCLOCK) are 5-V tolerant and provide integrated pullup resistors (typically 140 kΩ). Three 8-bit I2C registers provide individual enable control for each of the outputs. All outputs default to enabled at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit is written to the control register. The registers are write only and must be accessed in sequential order (i.e., random access of the registers is not supported). The CDC318A provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state. When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.

주요 특징

AI 번역
  • Output Skew, tsk(0), Less Than 250 ps
  • Pulse Skew, tsk(p); Less Than 500 ps
  • Supports up to Four Unbuffered SDRAM Dual Inline Memory Modules (DIMMs)
  • I2C Serial Interface Provides Individual Enable Control for Each Output
  • Operates at 3.3 V
  • Distributed Vcc and Ground Pins Reduce Switching Noise
  • 100-MHz Operation
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015
  • Packaged in 48-Pin Shrink Small Outline (DL) Package

응용 분야

AI 번역

PC applications