MICROCHIP ATMEGA1609-AFR

The ATmega808/809/1608/1609 microcontrollers are part of the megaAVR 0- series, which uses the AVR processor with hardware multiplier running at up to 20 MHz, and offers a wide range of Flash sizes up to 48 KB, up to 6 KB of SRAM, and 256 bytes of EEPROM in 28-, 32-, 40-, or 48-pin packages. The series uses the latest technologies from Microchip with a flexible and low-power architecture, including Event System and SleepWalking, accurate analog features, and advanced peripherals. The devices offer 8 or 16 KB in a 28/32/48-pin package.

• AVR@CPU:
  • Single-cycle I/O access
  • Two-level interrupt controller
  • Two-cycle hardware multiplier
• Memories:
  • 8 or 16 KB In-system self-programmable Flash memory
  • 256B EEPROM
  • 2 KB SRAM
  • Write/Erase endurance: Flash 10,000 cycles, EEPROM 100,000 cycles
  • Data retention: 40 years at 55°C
• System:
  • Power-on Reset (POR) circuit
  • Brown-out Detector (BOD)
  • Clock options: 16/20 MHz low-power internal oscillator, 32.768 kHz Ultra Low-Power (ULP) internal oscillator, 32.768 kHz external crystal oscillator, External clock input
  • Single-pin Unified Program Debug Interface (UPDI)
  • Three sleep modes: Idle with all peripherals running for immediate wake-up, Standby Configurable operation of selected peripherals, SleepWalking peripherals, Power-Down with limited wake-up functionality
• Peripherals:
  • One 16-bit Timer/Counter type A (TCA) with a dedicated period register and three compare channels
  • Up to four 16-bit Timer/Counters type B (TCB) with input capture
  • One 16-bit Real-Time Counter (RTC) running from an external crystal or an internal RC oscillator
  • Up to four USARTs with fractional baud rate generator, auto-baud, and start-of-frame detection
  • Master/slave Serial Peripheral Interface (SPI)
  • Master/slave TWI with dual address match, Can operate simultaneously as master and slave, Standard mode (Sm, 100 kHz), Fast mode (Fm, 400 kHz), Fast mode plus (Fm+, 1 MHz)
  • Event System for core independent and predictable inter-peripheral signaling