RENESAS 9DBV0241AKILF
| Hersteller | |
| Herst.-Teilenr. | 9DBV0241AKILF |
| LCSC-Nr. | C1542261 |
| Verp. | QFN-24-EP(4x4) |
| Kundennummer | |
| Hauptmerkm. | 1.7V~1.9V 200MHz 2 QFN-24-EP(4x4) Application Specific Clock/Timing RoHS |
| Datenblatt | RENESAS 9DBV0241AKILF |
| Alternativteile | 5 |
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | QFN-24-EP(4x4) | |
| Voltage - Supply | 1.7V~1.9V | |
| Features | Built-in phase-locked loop;Spread spectrum;Output enable/shutdown;Internal termination and bias network | |
| Operating Temperature | -40℃~+85℃ | |
| Output Frequency(Max) | 200MHz | |
| Number of outputs | 2 |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | QFN-24-EP(4x4) | |
| Voltage - Supply | 1.7V~1.9V |
| Typ | Beschreibung | |
|---|---|---|
| Features | Built-in phase-locked loop;Spread spectrum;Output enable/shutdown;Internal termination and bias network | |
| Operating Temperature | -40℃~+85℃ | |
| Output Frequency(Max) | 200MHz | |
| Number of outputs | 2 |
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Beschreibung
KI-Übersetzung
The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management.
Merkmale
KI-Übersetzung
- LP-HCSL outputs with Z0 = 100Ω; saves 8 resistors compared to standard HCSL outputs
- 35mW typical power consumption in PLL mode; reduced thermal concerns
- Spread Spectrum (SS) compatible; allows use of SS for EMI reduction
- OE# pins; support DIF power management
- HCSL compatible differential input; can be driven by common clock sources
- SMBus-selectable features; optimize signal integrity to application: slew rate for each output, differential output amplitude
- Pin/software selectable PLL bandwidth and PLL Bypass; optimize PLL to application
- Outputs blocked until PLL is locked; clean system start-up
- Device contains default configuration; SMBus interface not required for device control
- 3.3V tolerant SMBus interface; works with legacy controllers
- Space saving 24-pin 4x4mm VFQFPN; minimal board space
Anwendungen
KI-Übersetzung
- 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
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Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | QFN-24-EP(4x4) | |
| Voltage - Supply | 1.7V~1.9V | |
| Features | Built-in phase-locked loop;Spread spectrum;Output enable/shutdown;Internal termination and bias network | |
| Operating Temperature | -40℃~+85℃ | |
| Output Frequency(Max) | 200MHz | |
| Number of outputs | 2 |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | QFN-24-EP(4x4) | |
| Voltage - Supply | 1.7V~1.9V |
| Typ | Beschreibung | |
|---|---|---|
| Features | Built-in phase-locked loop;Spread spectrum;Output enable/shutdown;Internal termination and bias network | |
| Operating Temperature | -40℃~+85℃ | |
| Output Frequency(Max) | 200MHz | |
| Number of outputs | 2 |
Hilfe & FeedbackÄhnliche Produkte anzeigen (0) >
Beschreibung
KI-Übersetzung
The 9DBV0241 is a member of IDT's 1.8V Very-Low-Power (VLP) PCIe family. The device has 2 output enables for clock management.
Merkmale
KI-Übersetzung
- LP-HCSL outputs with Z0 = 100Ω; saves 8 resistors compared to standard HCSL outputs
- 35mW typical power consumption in PLL mode; reduced thermal concerns
- Spread Spectrum (SS) compatible; allows use of SS for EMI reduction
- OE# pins; support DIF power management
- HCSL compatible differential input; can be driven by common clock sources
- SMBus-selectable features; optimize signal integrity to application: slew rate for each output, differential output amplitude
- Pin/software selectable PLL bandwidth and PLL Bypass; optimize PLL to application
- Outputs blocked until PLL is locked; clean system start-up
- Device contains default configuration; SMBus interface not required for device control
- 3.3V tolerant SMBus interface; works with legacy controllers
- Space saving 24-pin 4x4mm VFQFPN; minimal board space
Anwendungen
KI-Übersetzung
- 1.8V PCIe Gen1/2/3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
C1542261 EasyEDA-Bibliothek
Compliance & Exportcodes
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Typ | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

