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MICROCHIP PIC18F27Q43-I/SS

Produttore
Cod. Prod.
PIC18F27Q43-I/SS
Cod. LCSC
C641880
Imballo
SSOP-28-208mil
Numero Cliente
Attr. chiave
Low-Power, High-Performance Microcontroller with XLP Technology
Scheda TecnicaMICROCHIP PIC18F27Q43-I/SS
Conformità RoHS2 documenti disponibili
Parti alternative5
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Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Embedded/Microcontrollers
ProduttoreMICROCHIP
ImballoSSOP-28-208mil
DAC (Bit)8bit
ADC (Bit)12bit
Number of I/O25
Operating Temperature-40℃~+85℃
Program Memory TypeFLASH
Voltage - Supply1.8V~5.5V
EEPROM1KB
Program Storage Size128KB
CPU CorePIC
Core Size8 Bit
CPU Maximum Speed64MHz
Oscillator TypeBuilt-in

Descrizione

Traduzione AI

The PIC18-Q43 microcontroller family is available in 28/40/44/48-pin devices for real-time control applications. This family features a 12-bit Analog-to-Digital Converter with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced capacitive touch sensing, averaging, filtering, oversampling and threshold comparison. This family showcases a new 16-bit Pulse-Width Modulator (PWM) module which provides dual independent outputs on the same time base. Additional features include vectored interrupt controller with fixed latency for handling interrupts, system bus arbiter, Direct Memory Access (DMA) capabilities, Universal Asynchronous Receiver-Transmitter (UART) with support for asynchronous, Digital Multiplex (DMX), Digital Addressable Lighting Interface (DALI) and Local Interconnect Network (LIN) protocols, Serial Peripheral Interface (SPI), I²C, memory features like Memory Access Partition (MAP) to support users in data protection and bootloader applications, and Device Information Area (DIA), which stores factory calibration values to help improve temperature sensor accuracy.

Caratteristiche

Traduzione AI
  • C Compiler Optimized RISC Architecture
  • Operating Speed:
    • DC – 64 MHz clock input
    • 62.5 ns minimum instruction cycle
  • Six Direct Memory Access (DMA) Controllers:
    • Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR spaces
    • User programmable source and destination sizes
    • Hardware and software triggered data transfers
  • Vectored Interrupt Capability:
    • Selectable high/low priority
    • Fixed interrupt latency of three instruction cycles
    • Programmable vector table base address
    • Backwards compatible with previous interrupt capabilities
  • 127-Level Deep Hardware Stack
  • Low-Current Power-on Reset (POR)
  • Configurable Power-up Timer (PWRT)
  • Brown-out Reset (BOR)
  • Low-Power BOR (LPBOR) Option
  • Windowed Watchdog Timer (WWDT):
    • Watchdog Reset on too long or too short interval between watchdog clear events
    • Variable prescaler selection
    • Variable window size selection