Nexperia 74LVC373APW/AU118

The 74LVC373A consists of eight D-type transparent latches, each with a separate D-type input and a three-state true output for bus-oriented applications. A latch enable input (pin LE) and an output enable input (pin OE) are shared by all internal latches. When pin LE is HIGH, data at the D inputs (pins D0 to D7) is entered into the latches. In this mode, the latches are transparent — that is, the latch outputs change each time their corresponding D inputs change. When pin LE is LOW, the latches store the information present at the D inputs one setup time prior to the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the eight latches are available at the Q outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs enter a high-impedance off state. Operation of pin OE does not affect the state of the latches. The inputs can be driven by 3.3V or 5V devices. When disabled, a voltage of up to 5.5V can be applied to the outputs. These features allow the devices to be used as translators in mixed 3.3V and 5V applications. The 74LVC373A is functionally identical to the 74LVC573A, but with a different pin arrangement.

• 5 V tolerant inputs/outputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• High-impedance outputs when V_CC = 0 V
• Complies with JEDEC standard:
  • JESD8-7A (1.65 V to 1.95 V)
  • JESD8-5A (2.3 V to 2.7 V)
  • JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
  • HBM JESD22-A114F exceeds 2000 V
  • MM JESD22-A115-B exceeds 200 V
  • CDM JESD22-C101E exceeds 1000 V
• Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃