TI DM74LS138M

These Schottky clamped circuits are designed for high-performance memory decoding or data routing applications requiring extremely short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the impact of system decoding. When used with high-speed memory, the delay times of these decoders are typically less than the memory's typical access time. This means the effective system delay introduced by the decoder is negligible. The DM74LS138 decodes one of eight outputs based on the states of three binary select inputs and three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when cascading. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. The enable inputs can be used as data inputs for demultiplexing applications. The DM74LS139 contains two independent 2-line to 4-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to their driving circuits. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and simplify system design.

• Designed for high-speed applications including memory decoders and data transmission systems
• DM74LS138 3-to-8 line decoder with 3 enable inputs, simplifying cascading and/or data reception
• DM74LS139 contains two fully independent 2-to-4 line decoders/demultiplexers
• Schottky-clamped for high performance
• Typical propagation delay (3-level logic) of 21 ns for both DM74LS138 and DM74LS139
• Typical power dissipation: 32 mW for DM74LS138, 34 mW for DM74LS139

• High-performance memory decoding
• Data routing
• Data transmission systems