MXIC MX66L1G45GMI-08G

MX66L1G45G is a 1Gb serial NOR Flash memory, internally organized as 134,217,728×8. In dual I/O or quad I/O mode, the architecture becomes 536,870,912 bits×2 or 268,435,456 bits×4. In single I/O mode, it operates on a simple 3-wire bus with three bus signals — SCLK, SI, and SO — with serial access enabled via CS#. In dual I/O read mode, SI and SO become SIO0 and SIO1; in quad I/O read mode, SI, SO, WP#, and NC become SIO0, SIO1, SIO2, and SIO3. Full-chip sequential read is supported. Once a program/erase command is issued, an automatic program/erase algorithm programs/erases and verifies the specified page or sector/block location. Programming is performed by byte, page (256 bytes), or word; erasing is performed by 4K-byte sector, 32K-byte block, 64K-byte block, or full chip. A status register indicates device status, with the WIP bit used to detect program or erase completion. When not in operation with CS# held high, the device remains in standby mode. Utilizing a proprietary memory cell, the device retains stored content after 100,000 program and erase cycles.

• Advanced sector protection function (Solid and Password Protect)
• Multi I/O Support - Single I/O, Dual I/O, and Quad I/O
• Supports DTR (Double Transfer Rate) Mode
• Supports clock frequencies up to 166MHz
• Quad Peripheral Interface (QPI) Read / Program Mode
• Supports Serial Peripheral Interface -- Mode 0 and Mode 3
• Single Power Supply Operation - 2.7 to 3.6 volts for read, erase, and program operations
• Protocol Support - Single I/O, Dual I/O and Quad I/O
• Latch-up protected to 100mA from -1V to Vcc + 1V
• Low Vcc write inhibit is from 2.3V to 2.5V
• Fast read for SPI mode - Supports Fast Read, 2READ, DREAD, 4READ, QREAD instructions
• Configurable dummy cycle number for fast read operation
• Supports Performance Enhance Mode - XIP (execute-in-place)
• Equal 4K byte sectors, or Equal Blocks with 32K bytes or 64K bytes each - Any Block can be erased individually
• Programming: 256byte page buffer - Quad Input/Output page program(4PP) to enhance program performance
• Typical 100,000 erase/program cycles
• 20 years data retention
• Input Data Format - 1-byte Command code
• Advanced Security Features - Block lock protection
• The BP0 - BP3 and T/B status bits define the size of the area to be protected against program and erase instructions