Infineon CY9BF324KQN-G-AVK1E2

The CY9B320M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost. These series are based on the Arm Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (USB, UART, CSIO, I2C, LIN).

• 32-bit Arm Cortex-M3 Core
• Processor version: r2p1
• Up to 72 MHz Frequency Operation
• Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
• 24-bit System timer (Sys Tick): System timer for OS task management
• Dual operation Flash memory
• Dual Operation Flash memory has the upper bank and the lower bank. So, this series could implement erase, write and read operations for each bank simultaneously.
• Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
• Work area: 32 Kbytes (lower bank)
• Read cycle: 0 wait-cycle
• Security function for code protection
• This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
• SRAM0: Up to 16 Kbytes
• SRAM1: Up to 16 Kbytes
• The USB interface is composed of Device and Host. PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.
• USB2.0 Full-Speed supported
• Max 6 EndPoint supported
• EndPoint 0 is control transfer
• EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer
• EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer
• EndPoint 1 to 5 are comprised of Double Buffers.
• The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64bytes
• Endpoint 1: 256bytes
• USB2.0 Full/Low-speed supported
• Bulk-transfer, interrupt-transfer and Isochronous-transfer support
• USB Device connected/dis-connected automatic detection
• Automatic processing of the IN/OUT token handshake packet
• Max 256-byte packet-length supported
• Wake-up function supported
• 4 channels with 16 steps ×9 -bit FIFO (ch.0/1/3/4), 4 channels without FIFO (ch.2/5/6/7)
• Operation mode is selectable from the followings for each channel.
• UART
• CSIO
• LIN
• I2C
• Full duplex double buffer
• Selection with or without parity supported
• Built-in dedicated baud rate generator
• External clock available as a serial clock
• Hardware Flow control : Automatically control the transmission/reception by CTS/RTS (only ch.4)
• Various error detection functions available (parity errors, framing errors, and overrun errors)
• Full duplex double buffer
• Built-in dedicated baud rate generator
• Overrun error detection function available
• LIN protocol Rev.2.1 supported
• Full duplex double buffer
• Master/Slave mode supported
• LIN break field generation (can be changed to 13 to 16-bit length)
• LIN break delimiter generation (can be changed to 1 to 4-bit length)
• Various error detection functions available (parity errors, framing errors, and overrun errors)
• Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps) supported
• The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
• 8 independently configured and operated channels
• Transfer can be started by software or request from the built-in peripherals
• Transfer address area: 32-bit (4 Gbytes)
• Transfer mode: Block transfer/Burst transfer/Demand transfer
• Transfer data type: byte/half-word/word
• Transfer block count: 1 to 16
• Number of transfers: 1 to 65536
• Successive Approximation type
• Built-in 2units
• R-2R type
• 10-bit resolution
• Operation mode is selectable from the followings for each channel.
• 16-bit PWM timer
• 16-bit PPG timer
• 16-/32-bit reload timer
• 16-/32-bit PWC timer
• This series can use its pins as general-purpose I/O ports when they are not used for peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function can be allocated to.
• Capable of pull-up control per pin
• Capable of reading pin level directly
• Built-in the port relocate function
• Up to 65 high-speed general-purpose I/O Ports @ 80 pin Package
• Some ports are 5V tolerant.
• The Dual Timer consists of two programmable 32-/16-bit down counters.
• Operation mode is selectable from the followings for each channel.
• Free-running Periodic (= Reload) One-shot
• The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.