Infineon S70FS01GSDSBHI213

The FS-S series devices are flash non-volatile memory products featuring MIRRORBIT™ technology (storing two bits of data per memory array transistor), Eclipse architecture (significantly improving program and erase performance), and 65nm photolithography. The series connects to host systems via SPI, supporting conventional SPI single-bit serial input/output (single I/O or SIO), with optional dual-bit (dual I/O or DIO) and quad-bit wide quad I/O (QIO) or QPI (Quad Peripheral Interface) serial commands. This multi-width interface is referred to as SPI multi-I/O or MIO. Additionally, QIO and QPI feature DDR read commands that transfer addresses and read data on both edges of the clock. The FS-S Eclipse architecture incorporates a page program buffer that allows programming of up to 512 bytes at a time.

• SPI with multiple I/O
• SPI clock polarity and phase modes 0 and 3
• DDR
• Extended addressing: 24-bit or 32-bit address options
• Serial command subset and package compatible with S25FL1-K, S25FL-P, and S25FL-S SPI families
• Multi-I/O command subset and package compatible with S25FL-P, S25FL1-K, and S25FL-S SPI families
• Read: commands include normal, fast, dual I/O, quad I/O, DDR quad I/O; modes include burst wrap, quad peripheral interface (QPI); supports Serial Flash Discoverable Parameters (SFDP) and Common Flash Interface (CFI) for configuration information
• Program: 256 or 512 byte page program buffer; program suspend and resume support; automatic ECC — internal hardware ECC corrects single-bit errors
• Erase: hybrid sector option (one group of eight 4 KB sectors and one 224 KB sector at top or bottom of address space, remaining sectors are 256 KB); uniform sector option (physically uniform 256 KB blocks); erase suspend and resume support; erase status evaluation support; minimum 100,000 program-erase cycles per sector; minimum 20-year data retention
• Security features: 1024-byte OTP array; block protection (status register bits control program or erase protection for contiguous sector ranges; hardware and software control options); Advanced Sector Protection (ASP) (individual sector protection controlled by boot code or password; optional password-controlled read access)
• Technology: 65 nm MIRRORBIT™ technology with Eclipse architecture
• Single supply voltage, CMOS I/O
• Voltage range 1.7 V to 2.0 V
• Temperature ranges: Industrial (-40°C to +85°C); Industrial Plus (-40°C to +105°C); Automotive AEC-Q100 Grade 3 (-40°C to +85°C); Automotive AEC-Q100 Grade 2 (-40°C to +105°C); Automotive AEC-Q100 Grade 1 (-40°C to +125°C)
• Packages (all lead-free): 16-pin SOIC 300 mil; BGA-24 6×8 mm; 5×5 ball package