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EDA-ModelleEasyEDA
MICROCHIP ZL30622LDF1
| Hersteller | |
| Herst.-Teilenr. | ZL30622LDF1 |
| LCSC-Nr. | C2669252 |
| Verp. | QFN-32-EP(5x5) |
| Kundennummer | |
| Hauptmerkm. | QFN-32-EP(5x5) Application Specific Clock/Timing RoHS |
| Datenblatt | MICROCHIP ZL30622LDF1 |
| RoHS-Konformität | 2 Dokumente verfügbar |
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | MICROCHIP | |
| Verp. | QFN-32-EP(5x5) | |
| Features | Non-volatile parameter storage |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | MICROCHIP |
| Typ | Beschreibung | |
|---|---|---|
| Verp. | QFN-32-EP(5x5) | |
| Features | Non-volatile parameter storage |
Hilfe & FeedbackÄhnliche Produkte anzeigen (0) >
Merkmale
KI-Übersetzung
- ITU-T G.813/G.8262 compliance (options 1 & 2)
- Programmable bandwidth, 0.1Hz to 500Hz
- Attenuates jitter up to several UI
- Freerun or holdover on loss of all inputs
- Hitless reference switching
- High-resolution holdover averaging
- Digitally controlled phase adjustment
- Three inputs, two differential/CMOS, one CMOS
- Any input frequency from 8kHz to 1250MHz (8kHz to 300MHz for CMOS)
- Per-input activity and frequency monitoring
- Automatic or manual reference switching
- Any output frequency from < 1 Hz to 1035MHz
- High-resolution fractional frequency conversion with 0ppm error
- Encapsulated design requires no external VCXO or loop filter components
- Output jitter as low as 0.25ps RMS (12kHz - 20MHz integration band)
- Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL
- In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
- Per-output supply pin with CMOS output voltages from 1.5V to 3.3V
- Precise output alignment circuitry and per output phase adjustment
- Per-output enable/disable and glitchless start/stop (stop high or low)
- Automatic self-configuration at power-up from internal EEPROM; up to four configurations pin-selectable
- Numerically controlled oscillator mode
- Input-to-output alignment with external feedback
- SPI or I²C processor Interface
- Easy-to-use evaluation software
- Very high-resolution DPLL architecture
- State machine automatically transitions between tracking and freerun/holdover states
- Revertive or nonrevertive reference selection algorithm
- Less than 0.1dB gain peaking
- Programmable phase-slope limiting
- Programmable tracking range (i.e. hold-in range)
- Truly hitless reference switching with < 200μs output clock phase transient
- Output phase adjustment in 10ps steps
- High-resolution frequency and phase measurement
- Fast detection of input clock failure and transition to holdover mode
- Holdover frequency averaging with programmable averaging time and delay time
- Very high-resolution fractional scaling (i.e. non-integer multiplication)
- Any-to-any frequency conversion with 0ppm error
- Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)
- Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter components
- Bypass mode supports system testing
- Three low-jitter output clocks
- Each output can be one differential output or two CMOS outputs
- Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs)
- In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin
- Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components
- Sophisticated output-to-output phase alignment
- Per-output phase adjustment with high resolution and unlimited range
- Per-output enable/disable
- Per-output glitchless start/stop (stop high or low)
- SPI or I²C serial microprocessor interface
- Automatic self-configuration at power-up from internal EEPROM memory; pin control to specify one of four stored configurations
- Numerically controlled oscillator (NCO) behavior allows system software to steer DPLL frequency with resolution better than 0.01ppb
- Input-to-output alignment with external feedback
- Four general-purpose I/O pins each with many possible status and control options
- Output frame sync signals: 2kHz or 8kHz (SONET/SDH), 1Hz (IEEE 1588) or other frequency
- Internal compensation for local oscillator frequency error
- Simple, intuitive Windows-based graphical user interface
- Supports all device features and register fields
- Makes lab evaluation of the ZL30622 quick and easy
- Generates configuration scripts to be stored in internal EEPROM
- Generates full or partial configuration scripts to be run on a system processor
- Works with or without a ZL30622 evaluation board
Anwendungen
KI-Übersetzung
- Telecom timing cards for SONET/SDH, SyncE, wireless base stations and other systems
Garantie auf jede Bestellung
100% Authentisch · 30-Tage-Rückgabe oder -Umtausch
Produktspezifikationen
Alle
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | MICROCHIP | |
| Verp. | QFN-32-EP(5x5) | |
| Features | Non-volatile parameter storage |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | MICROCHIP |
| Typ | Beschreibung | |
|---|---|---|
| Verp. | QFN-32-EP(5x5) | |
| Features | Non-volatile parameter storage |
Hilfe & FeedbackÄhnliche Produkte anzeigen (0) >
Merkmale
KI-Übersetzung
- ITU-T G.813/G.8262 compliance (options 1 & 2)
- Programmable bandwidth, 0.1Hz to 500Hz
- Attenuates jitter up to several UI
- Freerun or holdover on loss of all inputs
- Hitless reference switching
- High-resolution holdover averaging
- Digitally controlled phase adjustment
- Three inputs, two differential/CMOS, one CMOS
- Any input frequency from 8kHz to 1250MHz (8kHz to 300MHz for CMOS)
- Per-input activity and frequency monitoring
- Automatic or manual reference switching
- Any output frequency from < 1 Hz to 1035MHz
- High-resolution fractional frequency conversion with 0ppm error
- Encapsulated design requires no external VCXO or loop filter components
- Output jitter as low as 0.25ps RMS (12kHz - 20MHz integration band)
- Outputs are CML or 2xCMOS, can interface to LVDS, LVPECL, HSTL, SSTL and HCSL
- In 2xCMOS mode, the P and N pins can be different frequencies (e.g. 125MHz and 25MHz)
- Per-output supply pin with CMOS output voltages from 1.5V to 3.3V
- Precise output alignment circuitry and per output phase adjustment
- Per-output enable/disable and glitchless start/stop (stop high or low)
- Automatic self-configuration at power-up from internal EEPROM; up to four configurations pin-selectable
- Numerically controlled oscillator mode
- Input-to-output alignment with external feedback
- SPI or I²C processor Interface
- Easy-to-use evaluation software
- Very high-resolution DPLL architecture
- State machine automatically transitions between tracking and freerun/holdover states
- Revertive or nonrevertive reference selection algorithm
- Less than 0.1dB gain peaking
- Programmable phase-slope limiting
- Programmable tracking range (i.e. hold-in range)
- Truly hitless reference switching with < 200μs output clock phase transient
- Output phase adjustment in 10ps steps
- High-resolution frequency and phase measurement
- Fast detection of input clock failure and transition to holdover mode
- Holdover frequency averaging with programmable averaging time and delay time
- Very high-resolution fractional scaling (i.e. non-integer multiplication)
- Any-to-any frequency conversion with 0ppm error
- Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)
- Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter components
- Bypass mode supports system testing
- Three low-jitter output clocks
- Each output can be one differential output or two CMOS outputs
- Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs)
- In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin
- Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components
- Sophisticated output-to-output phase alignment
- Per-output phase adjustment with high resolution and unlimited range
- Per-output enable/disable
- Per-output glitchless start/stop (stop high or low)
- SPI or I²C serial microprocessor interface
- Automatic self-configuration at power-up from internal EEPROM memory; pin control to specify one of four stored configurations
- Numerically controlled oscillator (NCO) behavior allows system software to steer DPLL frequency with resolution better than 0.01ppb
- Input-to-output alignment with external feedback
- Four general-purpose I/O pins each with many possible status and control options
- Output frame sync signals: 2kHz or 8kHz (SONET/SDH), 1Hz (IEEE 1588) or other frequency
- Internal compensation for local oscillator frequency error
- Simple, intuitive Windows-based graphical user interface
- Supports all device features and register fields
- Makes lab evaluation of the ZL30622 quick and easy
- Generates configuration scripts to be stored in internal EEPROM
- Generates full or partial configuration scripts to be run on a system processor
- Works with or without a ZL30622 evaluation board
Anwendungen
KI-Übersetzung
- Telecom timing cards for SONET/SDH, SyncE, wireless base stations and other systems
C2669252 EasyEDA-Bibliothek
Compliance & Exportcodes
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Typ | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |