ISSI IS43DR86400C-25DBLI

ISSI's 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the 1/O balls. Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0 - BA1 select the bank; A0 - A12(x16) or A0 - A13(x8) select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location A0 - A9 for the burst access and to determine if the auto precharge A10 command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized.

• VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
• JEDEC standard 1.8V I/O (SSTL_18-compatible) Double data rate interface: two data transfers per clock cycle Differential data strobe (DQS, DQS) 4-bit prefetch architecture On chip DLL to align DQ and DQS transitions with CK
• 4 internal banks for concurrent operation
• Programmable CAS latency (CL) 3, 4, 5, and 6 supported
• Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength, full and reduced strength options
• On-die termination (ODT)