{"id":4329,"date":"2026-06-30T05:41:20","date_gmt":"2026-06-30T05:41:20","guid":{"rendered":"https:\/\/blogs.lcsc.com\/blog\/?p=4329"},"modified":"2026-06-30T05:41:20","modified_gmt":"2026-06-30T05:41:20","slug":"microvia-pcb-smt-technical-guide","status":"publish","type":"post","link":"https:\/\/blogs.lcsc.com\/blog\/microvia-pcb-smt-technical-guide\/","title":{"rendered":"Micro PCB &#038; Micro-SMT Assembly Technical Guide"},"content":{"rendered":"<h2><b><span data-font-family=\"Arial\">Takeaway<\/span><\/b><\/h2>\n<ul>\n<li><span data-font-family=\"Arial\"> Micro PCB: laser-drilled, \u2264150 \u00b5m finished diameter, aspect ratio \u22641:1 per IPC-2226 \u2014 connects adjacent layers only.<\/span><\/li>\n<li><span data-font-family=\"Arial\"> VIPPO (Via-in-Pad Plated Over): copper-filled via under BGA pad, planarized to \u00b110\u00a0\u00b5m \u2014 mandatory for BGA pitch \u22640.4\u00a0mm.<\/span><\/li>\n<li><span data-font-family=\"Arial\"> 01005 components (0.4\u00d70.2\u00a0mm, ~0.04\u00a0mg) require Type\u00a04\/5 solder paste, electroformed stencils, and \u00b130\u00a0\u00b5m @3\u03c3 placement accuracy.<\/span><\/li>\n<li><span data-font-family=\"Arial\"> Tombstoning root cause: asymmetric surface tension when one solder joint melts before the other \u2014 prevented by symmetric NSMD pads, balanced paste volume (3D SPI Cpk \u22651.33), and controlled soak at 180\u2013200\u00b0C.<\/span><\/li>\n<li><span data-font-family=\"Arial\"> BGA inspection chain: 3D SPI \u2192 3D AOI \u2192 AXI (&lt;5\u00a0\u00b5m resolution). IPC-7095 limits void area to \u226425\u00a0% per ball (Class\u00a02).<\/span><\/li>\n<li><span data-font-family=\"Arial\"> HDI stack-up options: 1+N+1 (0.5\u00a0mm BGA), 2+N+2 (0.4\u00a0mm BGA), 3+N+3\/Any-Layer (0.25\u20130.3\u00a0mm micro-BGA).<\/span><\/li>\n<li><span data-font-family=\"Arial\"> Supplier certifications to require: IPC-A-600\/6012 Class 3, IPC-A-610 Class 3, IPC-7095, ISO\u00a09001. Add IATF\u00a016949 for automotive; ISO\u00a013485 for medical.<\/span><\/li>\n<\/ul>\n<h2><b><span data-font-family=\"Arial\">What Are Micro <a href=\"https:\/\/www.lcsc.com\/pcba\">PCB\/SMT<\/a> Technologies?<\/span><\/b><\/h2>\n<p><span data-font-family=\"Arial\">\u201cMicro\u201d in PCB and SMT contexts covers a family of interconnected miniaturization technologies spanning three principal domains: micro components (passive and active SMD packages at 0201\/01005 scale and below), microvia PCBs (HDI boards using laser-drilled interconnects with diameter \u2264150\u00a0\u00b5m per IPC-2226), and micro-pitch assembly services (SMT lines capable of placing fine-pitch BGA, QFN, CSP, and chip components with sub-30\u00a0\u00b5m placement accuracy). Together these technologies form the enabling foundation for modern miniaturized electronics.<\/span><\/p>\n<p><span data-font-family=\"Arial\">Application domains for micro PCB\/SMT span the most demanding sectors of electronics manufacturing: consumer wearables and smartphones; 5G mmWave <a href=\"https:\/\/blogs.lcsc.com\/blog\/flex-rigid-flex-3d-pcbs-selction-guide\/\">RF<\/a> modules; medical implants and diagnostic equipment; ADAS automotive radar and vision processors; high-performance computing accelerators; and aerospace\/defense avionics. In every case, the driver is the same: maximum functionality per unit area while maintaining signal integrity, thermal reliability, and long-term product life.<\/span><\/p>\n<h2><b><span data-font-family=\"Arial\">How Micro PCB\/SMT Technologies Work<\/span><\/b><\/h2>\n<h4><b><span data-font-family=\"Arial\">Microvia HDI PCB Fabrication<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">Microvia PCB fabrication begins after standard inner-layer processing. Sequential build-up (SBU) lamination adds new dielectric and copper layers one pair at a time, each pair receiving its own laser-drilling and copper-plating cycle before the next lamination step. CO\u2082 or UV laser systems drill blind microvias with wall angles of 60\u201380\u00b0, creating a conical frustum profile that promotes complete electrolytic copper fill. Copper is plated at current densities of 20\u201330\u00a0ASF to form via wall thicknesses of 20\u201325\u00a0\u00b5m. After plating, vias are planarized using chemical-mechanical polishing (CMP) to maintain pad coplanarity within \u00b115\u00a0\u00b5m. The via fill factor is controlled to \u226595\u00a0%, eliminating internal voids that would otherwise reduce thermal conductivity and create stress concentration points during thermal cycling.<\/span><\/p>\n<h4><b><span data-font-family=\"Arial\">Micro-Component SMT Assembly<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">Micro-component placement requires a fundamentally different process window than standard 0402 or 0603 assembly. Pick-and-place machines for 01005 components require specialized vacuum nozzles (0.3\u20130.5\u00a0mm diameter), sub-30\u00a0\u00b5m @3\u03c3 placement accuracy, and machine-learning-enhanced vision systems for component recognition at magnifications where the part covers only a few hundred pixels. Solder paste for 01005 apertures uses Type\u00a04 or Type\u00a05 paste (particle size 20\u201338\u00a0\u00b5m or 15\u201325\u00a0\u00b5m respectively) with laser-cut or electroformed stencils featuring trapezoidal aperture profiles that improve paste release from stencil walls.<\/span><\/p>\n<p><span data-font-family=\"Arial\">Post-reflow inspection cannot rely on 2D AOI alone. 3D AOI with multi-angle illumination detects tombstoning, skew, and missing 01005 parts. 3D automated X-ray inspection (AXI) at resolution below 5\u00a0\u00b5m is required for BGA void analysis, ball collapse, and hidden bridging, with void quantification per IPC-7095 (maximum 25\u00a0% per ball for Class\u00a02). Statistical process control (SPC) with Cpk \u22651.33 for paste volume, placement offset, and reflow temperature provides the continuous quality data needed to sustain process capability on high-density mixed-technology boards.<\/span><\/p>\n<h2><b><span data-font-family=\"Arial\">Key Features and Advantages<\/span><\/b><\/h2>\n<table>\n<tbody>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><b><span data-font-family=\"Arial\">Feature<\/span><\/b><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"232\"><b><span data-font-family=\"Arial\">Description<\/span><\/b><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"218.66666666666666\"><b><span data-font-family=\"Arial\">Benefit<\/span><\/b><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">Ultra-High Routing Density<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"232\"><span data-font-family=\"Arial\">Microvias (&lt;150\u00a0\u00b5m) and stacked via structures increase trace channels and I\/O breakout per unit area<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"218.66666666666666\"><span data-font-family=\"Arial\">Enables routing of 0.25\u00a0mm pitch BGAs and 100+ I\/O CSPs without increasing layer count<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">Superior Signal Integrity<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"232\"><span data-font-family=\"Arial\">Shorter interconnects reduce parasitic inductance and capacitance; copper-filled vias eliminate stubs<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"218.66666666666666\"><span data-font-family=\"Arial\">Critical for SERDES, DDR5, and 5G mmWave requiring controlled impedance \u00b15\u00a0\u03a9<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">VIPPO \/ Via-in-Pad Capability<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"232\"><span data-font-family=\"Arial\">Microvias filled and plated under BGA pads with \u00b110\u00a0\u00b5m surface planarity<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"218.66666666666666\"><span data-font-family=\"Arial\">Prevents solder wicking; enables reliable assembly of 0.4\u00a0mm and 0.3\u00a0mm pitch BGAs<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">Micro-Component Placement Accuracy<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"232\"><span data-font-family=\"Arial\">Sub-30\u00a0\u00b5m @3\u03c3 pick-and-place with vision alignment handles 01005 and 0.2\u00a0mm pitch BGAs<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"218.66666666666666\"><span data-font-family=\"Arial\">Supports wearable, medical implant, and 5G module form factors impossible with standard assembly<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">Multi-Layer Stacked Microvia<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"232\"><span data-font-family=\"Arial\">Sequential lamination builds 1+N+1, 2+N+2, or any-layer HDI stack-ups with stacked blind\/buried vias<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"218.66666666666666\"><span data-font-family=\"Arial\">Vertical routing flexibility for complex SoC, FPGA, and AI accelerator package escape<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">Comprehensive Inspection Chain<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"232\"><span data-font-family=\"Arial\">3D SPI, 3D AOI, AXI (&lt;5\u00a0\u00b5m resolution), microsectioning, and electrical test per IPC-A-610\/IPC-7095<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"218.66666666666666\"><span data-font-family=\"Arial\">Ensures BGA joint quality, via fill, and micro-component placement all meet Class\u00a02\/3 standards<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2><b><span data-font-family=\"Arial\">Technical Specifications<\/span><\/b><\/h2>\n<h4><b><span data-font-family=\"Arial\">PCB Fabrication Parameters<\/span><\/b><\/h4>\n<table>\n<tbody>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><b><span data-font-family=\"Arial\">Parameter<\/span><\/b><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><b><span data-font-family=\"Arial\">Specification \/ Range<\/span><\/b><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Microvia diameter (laser-drilled)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">\u2264150\u00a0\u00b5m finished diameter; standard range 75\u2013150\u00a0\u00b5m (3\u20136\u00a0mil)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Minimum mechanical via (PTH)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">0.15\u00a0mm (6\u00a0mil) finished diameter<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Microvia aspect ratio (IPC-2226)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">\u22641:1 (depth not to exceed diameter)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Via fill factor<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">\u226595\u00a0% (copper or resin fill, void-free per X-ray)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">VIPPO surface planarity<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">\u00b110\u00a0\u00b5m after CMP planarization<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Layer-to-layer registration<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">\u00b125\u00a0\u00b5m (sequential lamination)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Minimum trace \/ space (HDI)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">2.5\u00a0mil \/ 2.5\u00a0mil (0.063\u00a0mm \/ 0.063\u00a0mm)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">PCB layer count<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">4\u201340 layers standard; up to 100 layers for specialty designs<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Board thickness range<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">0.13\u20137.0\u00a0mm<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Laser drilling system<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">CO\u2082 (large via, cost-effective) or UV (finer vias, better aspect ratio control)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Copper plating current density<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">20\u201330\u00a0ASF for via barrel; wall thickness 20\u201325\u00a0\u00b5m<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Surface finish options<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">ENIG, ENEPIG, Immersion Silver, OSP, Hard Gold<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">PCB certifications \/ Standards<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">IPC-A-600, IPC-6012, IPC-2226, IPC-4761, UL, ISO\u00a09001, RoHS, REACH<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h4><b><span data-font-family=\"Arial\">SMT Assembly Parameters<\/span><\/b><\/h4>\n<table>\n<tbody>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><b><span data-font-family=\"Arial\">Parameter<\/span><\/b><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><b><span data-font-family=\"Arial\">Specification \/ Range<\/span><\/b><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Micro-component minimum size<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">01005 (0.4\u00d70.2\u00a0mm, ~0.04\u00a0mg) imperial; 008004 metric<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">BGA minimum pitch (assembly)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">0.2\u00a0mm (sub-0.3\u00a0mm requires stacked microvias + VIPPO)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">SMT placement accuracy<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">\u00b130\u00a0\u00b5m @3\u03c3 (micro-BGA\/01005); \u00b135\u00a0\u00b5m (standard fine-pitch)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Solder paste type (01005)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Type\u00a04 (20\u201338\u00a0\u00b5m) or Type\u00a05 (15\u201325\u00a0\u00b5m) particle size<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Stencil type<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Electroformed nickel (micro-components); laser-cut SS (standard); step stencil (mixed height)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Reflow peak temperature (SAC305)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">235\u2013245\u00b0C; ramp rate &lt;3\u00b0C\/sec; time above liquidus 60\u201390\u00a0s<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Reflow temperature uniformity<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">\u00b12\u00b0C across board to prevent tombstoning of 01005 components<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Nitrogen atmosphere reflow<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">&lt;500\u00a0ppm O\u2082; reduces oxidation-related defects by up to 30\u00a0%<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">SPC control targets<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">Cpk \u22651.33 for paste volume, placement offset, and reflow temperature<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">BGA void acceptance (IPC-7095)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">\u226425\u00a0% void area per ball (Class\u00a02); stricter for Class\u00a03<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">SMT certifications \/ Standards<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"312\"><span data-font-family=\"Arial\">IPC-A-610, IPC-7095, IPC-7093, J-STD-020, RoHS<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2><b><span data-font-family=\"Arial\">HDI Stack-Up and Assembly Design Options<\/span><\/b><\/h2>\n<h3><b><span data-font-family=\"Arial\">Microvia PCB Stack-Up Configurations<\/span><\/b><\/h3>\n<h4><b><span data-font-family=\"Arial\">1+N+1 HDI<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">One build-up layer each side of the core. Supports 0.5\u00a0mm BGA escape with via-in-pad. Lowest cost HDI entry point; 5\u201310 business day prototype lead time. Typical applications: IoT modules, entry-level wearables, USB-C controller boards.<\/span><\/p>\n<h4><b><span data-font-family=\"Arial\">2+N+2 HDI<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">Two sequential build-up layers each side; required for 0.4\u00a0mm pitch BGA with staggered microvias. Supports DDR4\/DDR5 memory interfaces and mid-range SoC packages. Prototype lead time 10\u201315 days.<\/span><\/p>\n<h4><b><span data-font-family=\"Arial\">3+N+3 \/ Any-Layer HDI<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">Three or more build-up layers; stacked microvia columns connect any layer to any layer. Used for 0.25\u20130.3\u00a0mm pitch micro-BGAs in flagship smartphones, ADAS processors, and AI accelerator cards. Highest cost; longest lead time.<\/span><\/p>\n<h3><b><span data-font-family=\"Arial\">Via Types and Fill Options<\/span><\/b><\/h3>\n<ul>\n<li><span data-font-family=\"Arial\">Blind microvia: Surface layer to adjacent inner layer; CO\u2082 or UV laser drilled. Standard HDI building block.<\/span><\/li>\n<li><span data-font-family=\"Arial\">Buried microvia: Inner-layer-to-inner-layer; formed before outer lamination cycles. Preserves surface routing space.<\/span><\/li>\n<li><span data-font-family=\"Arial\">Stacked microvia: Vertically aligned blind vias; requires Cu fill of lower via before upper drilling. Maximum density; used for \u22640.3\u00a0mm pitch breakout.<\/span><\/li>\n<li><span data-font-family=\"Arial\">Staggered microvia: Offset vias between adjacent layers; more mechanically robust than stacked; preferred for 0.4\u00a0mm pitch designs.<\/span><\/li>\n<li><span data-font-family=\"Arial\">VIPPO \/ IPC-4761 Type VII: Copper-filled via capped and plated over in component pad; mandatory for BGA \u22640.4\u00a0mm pitch.<\/span><\/li>\n<li><span data-font-family=\"Arial\">Fill material options: Electrolytic copper fill (best thermal conductivity), conductive epoxy (silver or carbon), or non-conductive resin + copper cap.<\/span><\/li>\n<\/ul>\n<h3><b><span data-font-family=\"Arial\">SMT Assembly Service Scope<\/span><\/b><\/h3>\n<ul>\n<li><span data-font-family=\"Arial\">Component size range: 01005 passives through large connectors and power modules<\/span><\/li>\n<li><span data-font-family=\"Arial\">Package types handled: QFP, QFN, LGA, BGA, CSP, WLCSP, flip-chip, SiP, through-hole hybrid<\/span><\/li>\n<li><span data-font-family=\"Arial\">Mixed technology: SMT + PTH on same board; dual-side assembly with selective reflow<\/span><\/li>\n<li><span data-font-family=\"Arial\">Stencil options: Laser-cut SS (standard), electroformed Ni (micro-components), step stencil (mixed height components)<\/span><\/li>\n<li><span data-font-family=\"Arial\">Atmosphere: Air reflow (standard) or nitrogen (&lt;500\u00a0ppm O\u2082) for 01005\/fine-pitch BGA<\/span><\/li>\n<li><span data-font-family=\"Arial\">NPI\/DFM support: Gerber + BOM review, IPC-2221 pad design verification, thermal profiling, first-article inspection (FAI)<\/span><\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<h2><b><span data-font-family=\"Arial\">Application Scenarios by Industry<\/span><\/b><\/h2>\n<h4><b><span data-font-family=\"Arial\">Smartphones and Consumer Wearables<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">Modern flagship smartphones use any-layer HDI PCBs with stacked microvias to route hundreds of I\/Os from 0.35\u00a0mm pitch application processor packages. Smartwatches and fitness trackers rely on 01005 passives placed between BGA pins and 2+N+2 build-up stack-ups to achieve sub-1\u00a0mm board thickness while integrating PMIC, RF, sensor, and memory packages on a single rigid-flex assembly.<\/span><\/p>\n<h4><b><span data-font-family=\"Arial\">5G Infrastructure and mmWave Modules<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">5G sub-6\u00a0GHz and mmWave RF front-end modules (FEMs) require HDI PCBs with controlled impedance (\u00b15\u00a0\u03a9), low-loss dielectric materials (Rogers 4350B, Megtron 6), and micro-pitch flip-chip or WLCSP assembly with VIPPO pads. Antenna-in-Package (AiP) designs for 28\u00a0GHz and 39\u00a0GHz bands demand 2\u00a0mil\/2\u00a0mil trace\/space and placement accuracy below 15\u00a0\u00b5m for phased array element alignment.<\/span><\/p>\n<h4><b><span data-font-family=\"Arial\">Medical Implants and Diagnostic Equipment<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">Implantable cardiac devices, cochlear implants, and neural stimulators use 008004 and 01005 components on multi-layer rigid-flex PCBs to achieve the smallest possible implant volume. IPC-A-610 Class\u00a03 assembly standards apply, with 100\u00a0% X-ray inspection of all BGA joints and stringent biocompatibility requirements for encapsulation materials. Diagnostic imaging equipment uses high-layer-count HDI PCBs for FPGA-based signal processing with controlled-impedance DDR4\/DDR5 interfaces.<\/span><\/p>\n<h4><b><span data-font-family=\"Arial\">Automotive ADAS and EV Electronics<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">ADAS radar, camera, and LiDAR control units use automotive-grade HDI PCBs (AEC-Q200 components, \u221240\u00b0C to +125\u00b0C thermal cycling per IPC-TM-650 Method 2.6.7.2) with CTE-matched copper plating to prevent via fatigue. EV battery management systems (BMS) and on-board chargers integrate micro-pitch current sensing ICs in QFN packages demanding void-free solder joints per IPC-7093.<\/span><\/p>\n<h4><b><span data-font-family=\"Arial\">High-Performance Computing and AI Accelerators<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">Server motherboards, GPU boards, and AI accelerator cards use 2+N+2 or 3+N+3 HDI PCBs to route 1000+ ball HBM2e and GDDR6X memory packages with 0.65\u00a0mm and 0.5\u00a0mm pitch. PCIe Gen\u00a05 (32\u00a0GT\/s) and CXL 3.0 interfaces demand impedance-controlled microvia structures and back-drilling to eliminate via stubs that cause signal reflections at high data rates.<\/span><\/p>\n<h4><b><span data-font-family=\"Arial\">Aerospace and Defense Avionics<\/span><\/b><\/h4>\n<p><span data-font-family=\"Arial\">Avionics processors, guidance control systems, and satellite subsystems require HDI PCBs with strict tolerances for dielectric stability, Z-axis CTE, and blind via reliability across high-G shock and wide temperature ranges (\u221255\u00b0C to +125\u00b0C). IPC-6012 Class\u00a03\/A (space and military) specifications mandate enhanced copper plating thickness, X-ray and microsection quality verification, and full lot traceability.<\/span><\/p>\n<h3><b><span data-font-family=\"Arial\">Design and Procurement Guide<\/span><\/b><\/h3>\n<h4><b><span data-font-family=\"Arial\">Prototype and NPI Services<\/span><\/b><\/h4>\n<ul>\n<li><span data-font-family=\"Arial\">Prototype microvia PCBs: As few as 1\u20135 panels; 5\u201310 business days for 1+N+1 HDI; 10\u201315 days for 2+N+2 and beyond<\/span><\/li>\n<li><span data-font-family=\"Arial\">NPI engineering support: DFM review for HDI stack-up, VIPPO design verification, and BGA escape routing feasibility before tooling release<\/span><\/li>\n<li><span data-font-family=\"Arial\">First article inspection (FAI): 100\u00a0% microsection, X-ray, and electrical continuity on prototype lot before production release<\/span><\/li>\n<\/ul>\n<h4><b><span data-font-family=\"Arial\">Volume Production and Quality Systems<\/span><\/b><\/h4>\n<ul>\n<li><span data-font-family=\"Arial\">Flexible MOQ: Many HDI PCB suppliers accept orders from 1\u2013100 panels for prototypes, scaling to multi-thousand panel production with tiered pricing<\/span><\/li>\n<li><span data-font-family=\"Arial\">Lead time: Standard production 15\u201325 days; expedite options 7\u201310 days depending on layer count and via complexity<\/span><\/li>\n<li><span data-font-family=\"Arial\">In-process inspection: 3D SPI for paste volume, AOI after placement, real-time thermal profiling during reflow<\/span><\/li>\n<li><span data-font-family=\"Arial\">Final inspection: IPC-A-610 Class\u00a02\/3 visual + AOI, AXI for BGA, flying probe or ICT electrical test, microsection per IPC-TM-650\u00a02.1.1<\/span><\/li>\n<li><span data-font-family=\"Arial\">Reliability testing: Thermal cycling (\u221240\u00b0C to +125\u00b0C), HAST, IST interconnect stress testing, cross-section analysis<\/span><\/li>\n<\/ul>\n<h4><b><span data-font-family=\"Arial\">Supplier Certification Requirements<\/span><\/b><\/h4>\n<table>\n<tbody>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><b><span data-font-family=\"Arial\">Certification \/ Standard<\/span><\/b><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><b><span data-font-family=\"Arial\">Scope<\/span><\/b><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><b><span data-font-family=\"Arial\">When to Require<\/span><\/b><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">IPC-A-600 Class 2\/3<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">Bare PCB acceptability criteria<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">All HDI PCB orders<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">IPC-6012 Class 2\/3 (or 3\/A)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">PCB qualification and performance specification; 3\/A for military\/space<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">All HDI PCB orders; mandatory for defense\/space<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">IPC-A-610 Class 2\/3<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">Assembled board acceptability criteria<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">All SMT assembly orders<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">IPC-7095<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">BGA design and assembly process implementation; void acceptance criteria<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">Any BGA or micro-BGA assembly<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">IPC-2226<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">HDI PCB design standard<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">Reference for design; confirm supplier familiarity<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">ISO 9001:2015<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">Quality management system<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">All suppliers; baseline requirement<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">UL Recognition<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">North American safety compliance for PCB substrate<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">Products sold in North America<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">IATF 16949<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">Automotive quality management; PPAP documentation<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">Any automotive program (AEC-Q200 component traceability)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">ISO 13485<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">Medical device quality management system<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">Any medical device assembly; FDA 21 CFR Part 820 alignment<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"173.33333333333334\"><span data-font-family=\"Arial\">RoHS \/ REACH<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"237.33333333333334\"><span data-font-family=\"Arial\">Restricted substances compliance; halogen-free laminates and Pb-free solder<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"213.33333333333334\"><span data-font-family=\"Arial\">All programs (mandatory for EU; best practice globally)<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<h2><b><span data-font-family=\"Arial\">Technology Comparison: Microvia HDI vs. Standard PCB vs. Standard SMT<\/span><\/b><\/h2>\n<table>\n<tbody>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><b><span data-font-family=\"Arial\">Attribute<\/span><\/b><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><b><span data-font-family=\"Arial\">Microvia HDI + Micro SMT<\/span><\/b><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><b><span data-font-family=\"Arial\">Standard Multilayer PCB<\/span><\/b><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><b><span data-font-family=\"Arial\">Standard SMT (0402+)<\/span><\/b><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Minimum via diameter<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">50\u2013150\u00a0\u00b5m (laser-drilled)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">0.2\u20130.3\u00a0mm (mechanical drill)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">N\/A (board-level parameter)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Minimum component size<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">01005 (0.4\u00d70.2\u00a0mm) or 008004<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">0402 (1.0\u00d70.5\u00a0mm) typical<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">0402\u20130603 standard<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Minimum BGA pitch<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">0.2\u20130.3\u00a0mm (stacked VIPPO)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">0.8\u20131.0\u00a0mm (dog-bone fanout)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">0.8\u00a0mm (standard fan-out)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Routing density<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Very high (2.5\/2.5\u00a0mil)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Moderate (3.5\/3.5\u00a0mil)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Low\u2013moderate<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Board layer count<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">4\u201318+ (sequential lamination)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">4\u201316 (standard press)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Any<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Assembly accuracy required<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">\u00b115\u201330\u00a0\u00b5m @3\u03c3 (micro-BGA\/01005)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">\u00b175\u2013100\u00a0\u00b5m (standard SOP\/QFP)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">\u00b175\u2013100\u00a0\u00b5m<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Inspection requirement<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">3D AXI mandatory + 3D SPI + 3D AOI<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">2D AOI + spot X-ray<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">2D AOI (standard)<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Relative fabrication cost<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">High (sequential lamination, laser drill)<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Low\u2013moderate<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Low\u2013moderate<\/span><\/td>\n<\/tr>\n<tr>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Typical application<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Smartphones, medical implants, 5G, ADAS, HPC<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Industrial controls, power supplies, IoT<\/span><\/td>\n<td colspan=\"1\" rowspan=\"1\" width=\"156\"><span data-font-family=\"Arial\">Consumer electronics, general PCBs<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2><b><span data-font-family=\"Arial\">Frequently Asked Questions<\/span><\/b><\/h2>\n<h3><b><span data-font-family=\"Arial\">What is the difference between a microvia and a standard blind via?<\/span><\/b><\/h3>\n<p><span data-font-family=\"Arial\">A microvia is defined by IPC-2226 as a laser-drilled via with a finished diameter at or below 150\u00a0\u00b5m (6\u00a0mil) and an aspect ratio (depth-to-diameter) of 1:1 or less. Standard blind vias \u2014 which may be laser or mechanically drilled \u2014 can have diameters from 0.15\u00a0mm to 0.3\u00a0mm and may span two or more layers. Microvias are restricted to connecting only adjacent layers to maintain the 1:1 aspect ratio necessary for reliable copper fill. In HDI designs, multiple stacked or staggered microvias achieve connections spanning several layers, each individual via remaining within the microvia aspect ratio specification.<\/span><\/p>\n<h3><b><span data-font-family=\"Arial\">When should I use stacked microvias versus staggered microvias?<\/span><\/b><\/h3>\n<p><span data-font-family=\"Arial\">Stacked microvias \u2014 where via centers on adjacent build-up layers are vertically aligned \u2014 provide the highest routing density and are the only viable option for 0.25\u00a0mm and 0.3\u00a0mm pitch BGA breakout using inverted pyramid escape patterns. However, stacked microvias require complete copper fill of the inner via before the outer via can be drilled above it, adding lamination cycles and cost, and they concentrate thermal stress at the stacked column \u2014 making CTE-matched plating critical for reliability. Staggered microvias \u2014 offset vias between adjacent layers \u2014 are mechanically more robust, less prone to fatigue cracking during thermal cycling, and easier to plate reliably, requiring slightly more routing space. Industry-standard guidance: use staggered microvias where design pitch permits (generally 0.4\u00a0mm BGA and above), and reserve stacked microvias for 0.25\u20130.3\u00a0mm pitch devices where routing space is genuinely insufficient.<\/span><\/p>\n<h3><b><span data-font-family=\"Arial\">What causes tombstoning in 0201 and 01005 components, and how is it prevented?<\/span><\/b><\/h3>\n<p><span data-font-family=\"Arial\">Tombstoning occurs when one end of a two-terminal passive lifts vertically during reflow. The root cause is asymmetric surface tension: if one solder joint melts and wets before the other, the molten solder\u2019s surface tension exerts a rotational moment that stands the component upright. Contributing factors include pad asymmetry (unequal pad areas or different thermal mass), solder paste volume imbalance between the two pads, and thermal gradients across the board during the reflow soak zone. Prevention: non-solder mask defined (NSMD) pad designs with equal pad geometry; Type\u00a04 or Type\u00a05 solder paste with homogeneous printing verified by 3D SPI (target Cpk \u22651.33 for paste volume, CV &lt;10\u00a0%); symmetric component orientation relative to PCB travel direction; and a controlled soak stage at 180\u2013200\u00b0C to equalize board temperature before the reflow peak.<\/span><\/p>\n<h3><b><span data-font-family=\"Arial\">What inspection methods are mandatory for BGA and micro-BGA assemblies?<\/span><\/b><\/h3>\n<p><span data-font-family=\"Arial\">BGA and micro-BGA solder joints are hidden under the package body and cannot be reliably assessed by visual inspection or standard 2D AOI. The mandatory inspection chain for production assemblies is: 3D Solder Paste Inspection (3D SPI) before placement to verify paste volume and height at each BGA pad; 3D Automated Optical Inspection (3D AOI) after placement to confirm component alignment; and Automated X-ray Inspection (AXI or 3D AXI) after reflow to detect bridging, voiding, ball collapse, head-in-pillow (HiP), and missing balls. IPC-7095 defines acceptance criteria: for Class\u00a02 assemblies, void area per ball must not exceed 25\u00a0%. For micro-BGA at 0.3\u00a0mm pitch and below, AXI resolution must be below 5\u00a0\u00b5m to distinguish adjacent balls. Periodic microsectioning of production panels validates plating thickness, via fill quality, and intermetallic compound formation.<\/span><\/p>\n<h3><b><span data-font-family=\"Arial\">What certifications should I require from a micro PCB\/SMT service provider?<\/span><\/b><\/h3>\n<p><span data-font-family=\"Arial\">For a comprehensive micro PCB\/SMT procurement qualification, require: IPC-A-600 Class 2 or 3 for bare PCB acceptability; IPC-6012 Class 2 or 3 (Class 3\/A for military\/space) for PCB qualification; IPC-A-610 Class 2 or 3 for assembled board acceptability; IPC-7095 for BGA process implementation; IPC-2226 for HDI PCB design; ISO 9001:2015 for quality management; UL recognition for North American safety compliance; and RoHS\/REACH compliance documentation for halogen-free laminates and lead-free solder. Automotive programs, additionally require IATF 16949 certification and AEC-Q200 qualified component traceability. For medical devices, require ISO 13485 certification from the assembly provider and verification that their process has been qualified under FDA 21 CFR Part 820.<\/span><\/p>\n<h2><b><span data-font-family=\"Arial\">Conclusion<\/span><\/b><\/h2>\n<p><span data-font-family=\"Arial\">The choice of microvia HDI and micro-SMT technology is driven by component pitch, not preference. When your BGA pitch drops below 0.5\u00a0mm, standard dog-bone fanout runs out of space and you need microvias. The \u00a0pitch reaches 0.4 mm, VIPPO becomes mandatory to prevent solder wicking. When your passive component is 0201 or smaller, you need Type\u00a04\/5 paste, electroformed stencils, and a placement machine calibrated to sub-30\u00a0\u00b5m accuracy. These are not premium options \u2014 they are the minimum process requirements at those geometries.<\/span><\/p>\n<h2><b><span data-font-family=\"Arial\">Find What You Need on <a href=\"http:\/\/lcsc.com\">LCSC<\/a><\/span><\/b><\/h2>\n<p><span data-font-family=\"Arial\">LCSC Electronics stocks a comprehensive range of components for high-density micro-SMT designs \u2014 including 0201 and 01005 chip resistors and MLCC capacitors, fine-pitch QFN and LGA ICs, micro-BGA memory and processors, WLCSP RF devices, and precision passive components in automotive-grade (AEC-Q200) and industrial-grade packages. Whether you are populating a 2+N+2 HDI smartphone board, sourcing 01005 decoupling capacitors for a BGA power rail, specifying AEC-Q200 MLCC components for an ADAS sensor PCB, or building a BOM for a medical device with ISO 13485 traceability requirements, LCSC\u2019s parametric search lets you filter by package size, pitch, temperature rating, tolerance<\/span><span data-font-family=\"Arial\">.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Takeaway Micro PCB: laser-drilled, \u2264150 \u00b5m finished diameter, aspect ratio \u22641:1 per IPC-2226 \u2014 connects adjacent layers only. VIPPO (Via-in-Pad Plated Over): copper-filled via under BGA pad, planarized to \u00b110\u00a0\u00b5m \u2014 mandatory for BGA pitch \u22640.4\u00a0mm. 01005 components (0.4\u00d70.2\u00a0mm, ~0.04\u00a0mg) require Type\u00a04\/5 solder paste, electroformed stencils, and \u00b130\u00a0\u00b5m @3\u03c3 placement accuracy. Tombstoning root cause: asymmetric [&hellip;]<\/p>\n","protected":false},"author":3,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"categories":[177,175],"tags":[181,160],"class_list":["post-4329","post","type-post","status-publish","format-standard","hentry","category-pcb-techniques","category-pcb-smt","tag-pcb","tag-smt"],"blocksy_meta":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.8 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Micro PCB &amp; Micro-SMT Assembly Technical Guide Blog | LCSC Electronics<\/title>\n<meta name=\"description\" content=\"Master microvia PCB and micro-SMT assembly, then source micro-scale BOM components with real-time stock on LCSC.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/blogs.lcsc.com\/blog\/microvia-pcb-smt-technical-guide\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Micro PCB &amp; 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